The ability to dynamically reconfigure hardware is an idea with powerful possibilities, but it’s a concept that has been difficult to implement. Reconfigurability can be implemented in various ad hoc ways as well as with field programmable gate arrays (FPGA) and coarse-grained reconfigurable arrays (CGRA). These chips provide substantial computing resources with a tremendous number of logic gates and memory blocks, thus providing alternatives to traditional general-purpose central processing units (CPUs) and application-specific integrated circuits (ASICs). Rapid advances in semiconductor technology have made it possible to implement even more complex processing elements using reconfigurable logic, including FPGA-based system-on-a-chip (SoC) designs. In fact, FPGAs’ inherent reconfigurability remains beneficial in complex scenarios such as using hardware accelerators for various functions or coping with frequent design-requirement modifications. As a result, their popularity will continue into the future, particularly as we move toward 3D stacking forms of integration.
At the same time, power issues in modern processor design have become overwhelming and various efforts have been made to reduce the total power consumption of the chip. The well-known “dark silicon” problem points to the serious issue of power consumption of the chip due to both leakage and dynamic power. It is therefore expected that future processors will be limited by the power budget, which applies to programmable logic as well. Thus, the number of computing elements that can be actively powered on at any given time is severely limited, even though we can have many transistors on a single chip. This means the traditional CPU core, the reconfigurable logics, and the network-on-chip (NoC) fabric all require careful design to achieve the desired power efficiency.
The November 2014 issue of CN highlights four recently published articles on power issues in reconfigurable architectures. We selected this article set because it examines a range of computer architecture research projects that use reconfigurable logic, and thus offer a good introduction to the field.
With the first article, “Implications of the Power Wall: Dim Cores and Reconfigurable Logic,” authors Liang Wang and Kevin Skadron compare reconfigurable logic’s power efficiency versus that of CMP processors (which control power using voltage and frequency scaling) and ASIC accelerators at near-threshold voltage. The article shows the advantages of using reconfigurable logic, which can be efficiently configured into various forms of accelerators according to the application.
In “A Reconfigurable Architecture that Adapts to Physical Substrate Variations,” (PAnDA) James Alfred Walker and his colleagues propose a reconfigurable architecture that’s similar to FPGAs as far as the digital circuit reconfiguration is concerned, but provides additional features such as an analog layer for reconfiguring circuit characteristics. Using this feature, a design platform to reconfigure both analog and digital levels can be provided in the proposed PAnDA architecture.
“DPPC: Dynamic Power Partitioning and Control for Improved Chip Multiprocessor Performance,” by Kai Ma, Xiaorui Wang, and Yefu Wang, presents a power management method that considers both the processing cores and the last-level cache. The power budget is dynamically distributed over the chip including processing cores as well as the last-level cache. The decision is based on a dynamic model constructed online to measure the workload’s characteristics.
The final article, Randy W. Morris and his colleagues’ “Three-Dimensional Stacked Nanophotonic Network-on-Chip Architecture with Minimal Reconfiguration,” introduces an efficient reconfiguration algorithm for nanophotonic NoCs and 3D stacking that can dynamically control channel bandwidth according to data traffic. The paper also discusses proposed NoC architecture’s power efficiency.
Three outstanding practitioners and researchers from industrial organizations have graciously volunteered to contribute their opinions to this special section, and we thank them for it.
Ken Eguro of the Embedded and Reconfigurable Computing group at Microsoft Research in Redmond, Washington, discusses the problem of power dissipation and how technology scaling is reaching an end and thus compelling designers to introduce specialization in order to affordably yield computational power. He demonstrates how the advent of cloud computing is exacerbating this need for flexibility. Eguro also envisions what issues reconfigurable computing might encounter in the future, such as the integration and use of heterogeneous architectures. Some of his past and present research interests include applications of high-performance computing architectures, FPGA development and integration issues, and security concerns of hardware/security solutions using hardware. (For more details about Eguro, visit http://research.microsoft.com/en-us/people/eguro/)
Shaoshan Liu is a senior architect at Baidu USA working on big data infrastructure and Internet of Things technologies, and he also serves as a technology consultant to several major investment consulting firms. His prior experience includes working at LinkedIn, Microsoft Windows Phone, Microsoft Research, INRIA, Intel Research, and Broadcom. Over his years in industry, he has worked on nearly every layer of the technology stack, including hardware, firmware, operating systems, virtual machines, big data infrastructure, and mobile applications. In his video, Liu discusses FPGA use in industry — particularly how these reconfigurable hardware approaches offer efficient solutions in the context of highly parallel big data workloads, which are computationally intensive and power hungry. He also broaches the use of FPGAs as one of the building blocks in heterogeneous computing nodes. (For more details about Liu, visit https://www.linkedin.com/in/shaoshanliu.)
Sunil Shukla is a research staff member at the IBM T.J. Watson Research Center. His research focuses on reconfigurable accelerator architectures, such as FPGAs and CGRAs, and their programming models. His video explains how we have benefitted from Dennard’s scaling and Moore’s law in the past, and the aftermath of the scaling laws, which are nearing their end. Shukla discusses the role heterogeneous accelerator-rich computing will play in the future as power dissipation becomes the primary concern and concludes by showing evidence of the use of reconfigurable accelerators in the server markets. (For more details about Shukla, visit http://researcher.watson.ibm.com/researcher/view.php?person=us-skshukla)
These four theme articles highlight but some of the current research directions in the field. If you’re looking for further insights on research related to reconfigurable computing, several IEEE Computer Society magazines and transactions have published special issues on the topic. For instance, IEEE Micro ran an issue focus on reconfigurable computing in its January-February 2014 issue. Power-aware reconfigurable architecture is an exciting research area. It will have significant impact on the design of future-generation processors and computing elements. Do you agree that the future many-core architecture will be implemented as an accelerator-rich heterogeneous architecture? We invite you to dig into the wealth of possibilities by starting from the articles in this month’s theme.
W.W. Ro, C. Liu, and J.-L. Gaudiot, “Reconfigurability and Power Issues in Computer Systems Design,” Computing Now, vol. 7, no. 11, November 2014, IEEE Computer Society [online]; http://www.computer.org/publications/tech-news/computing-now/reconfigurability-and-power-issues-in-computer-systems-design.
Won Woo Ro is an associate professor in the School of Electrical and Electronic Engineering at Yonsei University, Seoul, Korea. He has a PhD from the University of Southern California. His research interests include microprocessor architecture, GPU architecture, and parallel computing. Contact him at firstname.lastname@example.org.
Chen Liu is an assistant professor in the Department of Electrical and Computer Engineering at Clarkson University. He has a PhD from the University of California, Irvine. His technical interests include computer architecture, high performance computing, and hardware acceleration for scientific computing. Contact him at email@example.com.
Jean-Luc Gaudiot is a professor in the Department of Electrical Engineering and Computer Science at the University of California, Irvine. He has a PhD from the University of California, Los Angeles. His technical interests include parallel computing, microarchitecture, and reconfigurable architectures. Contact him at firstname.lastname@example.org.