HRL: Efficient and flexible reconfigurable logic for near-data processing
FEB 16, 2017 16:28 PM
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HRL: Efficient and flexible reconfigurable logic for near-data processing

HRL: Efficient and flexible reconfigurable logic for near-data processing

Mingyu Gao, Stanford University
Christos Kozyrakis, Stanford University

This paper presents Heterogeneous Reconfigurable Logic (HRL), a reconfigurable array for near-data-processing systems that improves on both fine-grained and coarse-grained reconfigurable logic arrays.

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