Nomination Deadline:Deadline: 1 June 2023 - 11:59PM EDT
The award nomination requires a minimum of 3 endorsements by the award deadline.
Nomination Questions (pdf) | Download Call for Nominations_2022 (pdf) | Press Release
Next Deadline: 1 June 2023 – 11:59 pm EDT (USA)
The B. Ramakrishna Rau award will be presented “in recognition of substantial contributions in the field of computer microarchitecture and compiler code generation.”
The candidate will have made an outstanding, innovative contribution or contributions to microarchitecture, use of novel microarchitectural techniques or compiler/architecture interfacing. It is hoped, but not required, that the winner will have also contributed to the computer microarchitecture community through teaching, mentoring, or community service. This award will consist of a certificate and a $2,000 honorarium.
The winner will be announced and invited to present a paper and/or presentation at the ACM/IEEE International Symposium on Microarchitecture. The Rau award will be presented annually and honored to a single recipient.
2023 B. Ramakrishna Rau Award Committee Chair
Daniel A. Jiménez, Texas A&M University
For contributions to compiler technology for instruction-level parallelism and application-specific architectures.
For contributions to neural branch prediction in microprocessors.
For pioneering contributions to cache design and branch prediction.
For contributions to branch prediction in processors, microarchitecture techniques in heterogeneous processing, microarchitecture support for virtual machines, and near-memory processing.
For contributions to compiler techniques and microarchitectures for instruction-level and thread-level parallel computing.
For pioneering techniques enabling instruction-level parallelism and speculative multithreading via cooperative resource scheduling between offline compiler and runtime micro-architecture elements.
For contributions to critical analysis of microarchitecture and the development of the Pentium Pro processor.
For contributions to Instruction Level Parallelism technology, including compiler optimization, program representation, microarchitecture, and applications.
For contributions to VLIW, instruction-level-parallelism, binary translation,Java performance, and service to the community
For the development of trace scheduling compilation and pioneering work in VLIW (Very Long Instruction Word) architectures.
For significant contributions and inspiring leadership in the microarchitecture community with respect to teaching, mentoring, research, and service.