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Gurindar (Guri) Sohi

Award Recipient

Featured ImageGurindar (Guri) Sohi grew up in India and did his undergraduate studies at the Birla Institute of Technology and Science (BITS), in Pilani, India before coming to the United States for graduate studies. In August 1981 he started as a research assistant at the University of Illinois under the mentorship of Professor Edward Davidson.

After receiving his PhD in 1985, got the opportunity to join the faculty of the Computer Sciences Department at the University of Wisconsin-Madison where he had the opportunity to work with an outstanding group of graduate students over the years. He progressed through the academic ranks and is currently a Vilas Research Professor and a John P. Morgridge Professor. He served as Chair of the Computer Sciences Department from 2004 until 2008 and again from 2017 until 2019.

Sohi's research has been in the design of high-performance microprocessors and computer systems. His initial research efforts in instruction-level parallel processors, done at a time when it went against the mainstream of though in processor architecture, benefited greatly from the encouragement and mentorship of Professor Jim Smith. Results from his research over the years can be found in almost every high-end microprocessor in the market today. He has taught classes ranging from  introductory freshmen to advanced graduate courses, supervised 22 PhD students, and performed a variety of service roles.

He received the 1999 ACM SIGARCH Maurice Wilkes award and the 2011 ACM/IEEE Eckert-Mauchly. At Wisconsin he was selected as a Vilas Associate in 1997, a WARF Kellett Mid-Career Faculty Researcher in 2000, a WARF Named Professor in 2007, and a Vilas Research Professor in 2015. He is a Fellow of both the ACM and the IEEE and was elected to the National Academy of Engineering in 2009 and the American Academy of the Arts and Sciences in 2018.

Awards

2025 IEEE Computer Society Computer Pioneer in Honor of the Women of ENIAC Award
“For contributions to the microarchitecture of instruction-level parallel processors and his impact on the computer architecture community.”
Learn more about the Computer Pioneer in Honor of the Women of ENIAC Award

2016 B. Ramakrishna Rau Award
“For pioneering techniques enabling instruction-level parallelism and speculative multithreading via cooperative resource scheduling between offline compiler and runtime micro-architecture elements.”
Learn more about the B. Ramakrishna Rau Award

2011 Eckert-Mauchly Award
“For pioneering widely used micro-architectural techniques for instruction-level parallelism.”
Learn more about the Eckert-Mauchly Award

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