Gurindar (Guri) Sohi has been on the faculty at the University of Wisconsin-Madison since 1985, where he is currently the John P. Morgridge Professor and the E. David Cronon Professor of Computer Sciences. He served as the chair of the Computer Sciences Department from 2004–2008.
Over the years his work has focused on innovative techniques for fine-grain and instruction-level parallelism in high-performance microprocessors. Many of his direction-changing innovations have gone on to become defining characteristics of important commercial microprocessors.
Sohi’s proposal for an out-of-order execution model with precise exceptions and speculative execution has served as the basis for many commercial superscalar microprocessors that have been designed and built since the early 1990s and are now ubiquitous. His proposal for thread-level speculation significantly influenced thinking about parallel processor models and served as the inspiration for several microprocessor designs, including Sun’s MAJC and Rock. His work on memory dependence prediction led to a rethinking of decades-old knowledge on how to process memory operations out of order. He has made numerous other contributions to the field of computer architecture.
In 1999 Sohi received the ACM SIGARCH Maurice Wilkes award. At Wisconsin he was selected a Vilas Associate (1997), a WARF Kellett Mid-Career Faculty Researcher (2000), and a WARF Named Professor (2007). A Fellow of both the ACM and the IEEE, he was inducted into the National Academy of Engineering in 2009.
Sohi was born in 1960 in Patiala, India. After his undergraduate education at the Birla Institute of Technology and Science (BITS) in Pilani, India, he came to the United States to study at the University of Illinois, Urbana-Champaign, where he graduated with an MS (1983) and a PhD (1985).
The Rau Award Presentations
Professor Sohi receiving the 2016 Rau Award from Kemal Ebcioğlu, Rau Committee Member. The ceremony was held at MICRO 49 — TAIWAN on 18 October 2016.
2011 Eckert-Mauchly Award
“For pioneering widely used micro-architectural techniques for instruction-level parallelism.”
Learn more about the Eckert-Mauchly Award