Biography

Dr. Joel S. Emer is an Intel Fellow working in the Digital Enterprise Group, where he is director of micro-architecture research. Before joining Intel he spent 22 years as a Digital/Compaq employee, where he worked on processor architecture, performance analysis and performance modeling methodologies for a number of VAX and Alpha CPUs.

He is widely recognized for his architecture contributions to various VAX and Alpha processors, also for pioneering efforts in simultaneous multithreading, for his analysis of the architectural impact of soft errors and for his seminal work on the now pervasive quantitative approach to processor evaluation. He also has researched heterogeneous distributed systems and networked file systems at DEC and during a three year sabbatical at MIT. His current research interests include processor reliability, multithreaded processor organizations, techniques for increased instruction level parallelism, pipeline organization, instruction and data cache organizations, branch prediction schemes, and performance modeling.

Dr. Emer holds a Ph.D. in Electrical Engineering from the University of Illinois, and M.S.E.E. and B.S.E.E. degrees from Purdue University. He is a senior visiting lecturer in MIT since 2005. He holds over 20 patents and has published more than 30 papers. He is also a Fellow of both the ACM and the IEEE.