Joel S. Emer

Award Recipient
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Joel Emer is a professor of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology and spends part time as a Senior Distinguished Research Scientist in Nvidia’s Architecture Research group. Previously, he worked at Intel where he was an Intel Fellow and Director of Microarchitecture Research.  Earlier, he worked at Compaq and Digital Equipment Corporation. He earned a doctorate in electrical engineering from the University of Illinois in 1979. He received a bachelor’s degree with highest honors in electrical engineering in 1974, and his master’s degree in 1975 — both from Purdue University.

Over his career, he has held research and advanced development positions investigating processor microarchitecture and developing performance modeling and evaluation techniques. He has made key architectural contributions to a number of VAX, Alpha and X86 processors and is recognized as a pioneering developer of the widely employed quantitative approach to processor performance evaluation, including creation of the “Iron Law of Processor Performance”.  He is also well known for his contributions to the advancement of deep learning accelerator design, spatial and parallel architectures, processor reliability analysis, cache organization and simultaneous multithreading.

Recognitions of his contributions include “Most Influential Paper Awards” for his work on simultaneous multithreading and reliability analysis, and six of his papers have been selected as IEEE Micro’s Top Picks in Computer Architecture. Five of his papers have been identified as among the “most significant” of the second 25 years of ISCA, and he has the most “most cited” papers of the first 50 years of ISCA. Among his professional honors, he is a Fellow of the ACM and IEEE, and a member of the NAE. He is a member of the ISCA, MICRO, and ASPLOS Halls of Fame, and the Computer Architecture Aggregated Hall of Fame. In 2009, he was recipient of the Eckert-Mauchly award for lifetime contributions in computer architecture.


2023 B. Ramakrishna Rau Award Recipient
“For pioneering contributions to microarchitectural analysis, microarchitecture features, and for bringing clarity to the field with fundamental concepts and terminology.”
Learn more about the B. Ramakrishna Rau Award


2009 Eckert-Mauchly Award Recipient
“For pioneering contributions to performance analysis and modeling methodologies; for design innovations in several significant industry microprocessors; and for deftly bridging research and development, academia and industry.”
Learn more about the Eckert-Mauchly Award