IEEE Transactions on Services Computing
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From the April-June 2018 issue
The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores
By Igor Loi, Alessandro Capotondi, Davide Rossi, Andrea Marongiu, and Luca Benini
High performance and extreme energy efficiency are strong requirements for a fast-growing number of edge-node Internet of Things (IoT) applications. While traditional Ultra-Low-Power designs rely on single-core micro-controllers (MCU), a new generation of architectures leveraging fully programmable tightly-coupled clusters of near-threshold processors is emerging, joining the performance gain of parallel execution over multiple cores with the energy efficiency of low-voltage operation. In this work, we tackle one of the most critical energy-efficiency bottlenecks for these architectures: instruction memory hierarchy. Exploiting the instruction locality typical of data-parallel applications, we explore two different shared instruction cache architectures, based on energy-efficient latch-based memory banks: one leveraging a crossbar between processors and single-port banks (SP), and one leveraging banks with multiple read ports (MP). We evaluate the proposed architectures on a set of signal processing applications with different executable sizes and working-sets. The results show that the shared cache architectures are able to efficiently execute a much wider set of applications (including those featuring large memory footprint and irregular access patterns) with a much smaller area and with much better energy efficiency with respect to the private cache. The multi-port cache is suitable for sizes up to a few kB, improving performance by up to 40 percent, energy efficiency by up to 20 percent, and energy × area efficiency by up to 30 percent with respect to the private cache. The single-port solution is more suitable for larger cache sizes (up to 16 kB), providing up to 20 percent better energy × area efficiency than the multi-port, and up to 30 percent better energy efficiency than private cache.
Editorials and Announcements
- The winner of the 2017 Best TMSCS Paper Award is:
"Enabling New Computation Paradigms with HyperFET - An Emerging Device"
by Wei-Yu Tsai, Xueqing Li, Matthew Jerry, Baihua Xie, Nikhil Shukla, Huichu Liu, Nandhini Chandramoorthy, Matthew Cotter, Arijit Raychowdhury, Donald M Chiarulli, Steven P Levitan, Suman Datta, John Sampson, Nagarajan Ranganathan, Vijaykrishnan Narayanan
IEEE Transactions on Multi-Scale Computing Systems, Vol. 2, Iss. 1, pp. 30-48, 2016.
- We're pleased to announce that Partha Pratim Pande, professor at Washington State University, has accepted the position of inaugural Editor-in-Chief.
- Editorial (April-June 2017)
- Editorial (Jan-March 2016)
- Introduction to IEEE Transactions on Multiscale Computing Systems (TMSCS) (Jan-March 2015)
- Welcome Message (Jan-March 2015)
- Guest Editorial: Emerging Technologies and Architectures for Manycore Computing Part 1: Hardware Techniques (April-June 2018)
- Guest Editorial: Special Issue on Accelerated Computing (January-March 2018)
- Design and Applications of Neuromorphic Computing System (Oct-Dec 2016)
- Hardware/Software Cross-Layer Technologies for Trustworthy and Secure Computing (July-Sept 2016)
- Emerging Memory Technologies—Modeling, Design, and Applications for Multi-Scale Computing (July-Sept 2015)
- Wearables, Implants, and Internet of Things (April-June 2015)
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