IEEE Transactions on Computers
IEEE Transactions on Computers (TC) is a monthly publication that publishes research in such areas as computer organizations and architectures, digital devices, operating systems, and new and important applications and trends.
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From the May 2017 issue
Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache
By Xunchao Chen, Navid Khoshavi, Ronald F. DeMara, Jun Wang, Dan Huang, Wujie Wen, and Yiran Chen
For the sake of higher cell density while achieving near-zero standby power, recent research progress in Magnetic Tunneling Junction (MTJ) devices has leveraged Multi-Level Cell (MLC) configurations of Spin-Transfer Torque Random Access Memory (STT-RAM). However, in order to mitigate the write disturbance in an MLC strategy, data stored in the soft bit must be restored back immediately after the hard bit switching is completed. Furthermore, as the result of MTJ feature size scaling, the soft bit can be expected to become disturbed by the read sensing current, thus requiring an immediate restore operation to ensure the data reliability. In this paper, we design and analyze a novel Adaptive Restore Scheme for Write Disturbance (ARS-WD) and Read Disturbance (ARS-RD), respectively. ARS-WD alleviates restoration overhead by intentionally overwriting soft bit lines which are less likely to be read. ARS-RD, on the other hand, aggregates the potential writes and restore the soft bit line at the time of its eviction from higher level cache. Both of these two schemes are based on a lightweight forecasting approach for the future read behavior of the cache block. Our experimental results show substantial reduction in soft bit line restore operations, delivering 17.9 percent decrease in overall energy consumption and 9.4 percent increase in IPC, while incurring negligible capacity overhead. Moreover, ARS promotes advantages of MLC to provide a preferable L2 design alternative in terms of energy, area and latency product compared to SLC STT-RAM alternatives.
Editorials and Announcements
Editor's pick of the year 2016 (4 selected papers, each one free-to-download for three months in 2017)
- (January-March 2017) - Memory Bandwidth Management for Efficient Performance Isolation in Multi-Core Platforms, by Heechul Yun, Gang Yao, Rodolfo Pellizzoni, Marco Caccamo, and Lui Sha (IEEE Transactions on Computers, Volume: 65, Issue: 2, February 2016, pages 562-576, DOI: 10.1109/TC.2015.2425889).
- (April-June 2017) - Conﬁgurable XOR Hash Functions for Banked Scratchpad Memories in GPUs, by Gert-Jan van den Braak, Juan Gomez-Luna, Jose Marıa Gonzalez-Linares, Henk Corporaal, and Nicolas Guil (IEEE Transactions on Computers, Volume: 65, Issue: 7, July 2016, pages 2045-2058, DOI: 10.1109/TC.2015.2479595).
- (July-September 2017) - Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption, by Xiaolin Cao, Ciara Moore, Maire O’Neill, Elizabeth O’Sullivan, and Neil Hanley (IEEE Transactions on Computers, Volume: 65, Issue: 9, September 2016, pages 2794-2806, DOI: 10.1109/TC.2015.2498606).
- (September-December 2017) - A New Design of In-Memory File System Based on File Virtual Address Framework by Edwin H.-M. Sha, Xianzhang Chen, Qingfeng Zhuge, Liang Shi, and Weiwen Jiang (IEEE Transactions on Computers, Volume: 65, Issue: 10, October 2016, pages 2959-2972, DOI: 10.1109/TC.2016.2516019).
- Editor's pick of the year selection, announced in the July 2016 Editorial
- Multimedia presentations of each monthly featured paper are now available in Chinese, English and Spanish
- Get Your Journals as eBooks for Free
- Special Section on Cryptographic Engineering in a Post-Quantum World
Extended Deadline: May 31, 2017
- Special Section on Advanced Techniques for Efficient and Reliable Cloud Storage (August 2016)
- Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems (April 2016)
- IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (March 2016)
New Essential Set
- "Cloud Computing" available at computer.org/store
- "Industrial Implementations of Floating-Point Units" available at computer.org/store
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A Message from Editor-in-Chief Paolo Montuschi
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