IEEE Computer Architecture Letters

IEEE Computer Architecture Letters (CAL) is a semi-annual forum for fast publication of new, high-quality ideas in the form of short, critically refereed, technical papers. Submissions are welcomed on any topic in computer architecture.

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From the January-June 2017 issue

LA-LLC: Inter-Core Locality-Aware Last-Level Cache to Exploit Many-to-Many Traffic in GPGPUs

By Xia Zhao, Yuxi Liu, Almutaz Adileh, and Lieven Eeckhout

Featured article thumbnail imageThe reply network is a severe performance bottleneck in General Purpose Graphic Processing Units (GPGPUs), as the communication path from memory controllers (MC) to cores is often congested. In this paper, we find that instead of relying on the congested communication path between MCs and cores, the unused core-to-core communication path can be leveraged to transfer data blocks between cores. We propose the inter-core Locality-Aware Last-Level Cache (LA-LLC), which requires only few bits per cache block and enables a core to fetch shared data from another core's private cache instead of the LLC. Leveraging inter-core communication, LA-LLC transforms few-to-many traffic to many-to-many traffic, thereby mitigating the reply network bottleneck. For a set of applications exhibiting varying degrees of inter-core locality, LA-LLC reduces memory access latency and increases performance by 21.1 percent on average and up to 68 percent, with negligible hardware cost.

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Editorials and Announcements


  • We are pleased to announce that Daniel Sorin, the W.H. Gardner Jr. Professor of Electrical and Computer Engineering at Duke University, Durham, North Carolina, USA, has been named the new Editor-in-Chief of the IEEE Computer Architecture Letters starting in 2017.

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