Peter M. Kogge

2012 Seymour Cray Award Recipient

"For innovations in advanced computer architecture and systems."

Peter Kogge


Peter Kogge is an architect and designer of massively parallel systems, with an emphasis on memory as their centerpiece. Many of these systems were the first or second of their kind, and often for non-traditional applications His election to IEEE Fellow in 1990 and to IBM Fellow in 1993 were for contributions to high-performance computing.

Dr. Kogge received his B.S. in E.E from the Univ. of Notre Dame in 1968, M.S. in Systems and Information Sciences from Syracuse Univ. in 1970, and a Ph.D. in E.E. from Stanford Univ. in 1973. His Ph.D. thesis on the parallel solution of recurrence problems was one of the earliest on parallel prefix, and as a special case led to the Kogge-Stone adder, used today throughout industry as a primary design for high performance adders.

From 1968 until 1994 he was with IBM's Federal Systems Division, where he designed the world's second multi-threaded processor (after Cray's I/O processor in the CDC 6600) which flew on every Space Shuttle launch as part of perhaps the first parallel processor to fly in space. He also designed the IBM 3838 Attached Array processor which for a time was the fastest single precision floating point processor marketed by IBM. In the late 1980s he started several projects focused on moving computation closer into the memory system, culminating in the EXECUBE chip, perhaps the world's first multi-core chip and implemented on a DRAM die. EXECUBE supported 8 separate 16 bit cores that could run in both MIMD and a modified SIMD mode, and could be gluelessly expanded into multi-chip systems. A development system in 1994 supported 64 such chips, for a 512 node system in the space of a workstation.

In 1977 Dr. Kogge was a visiting faculty at the Univ. of Massachusetts, and after that until 1994 he was also adjunct faculty on the CS department of the State University of New York at Binghamton. In 1994 he joined the Univ. of Notre Dame as the first holder of the Ted McCourtney Endowed chair in the Computer Science and Engineering Dept. While at Notre Dame he also was the Interim Schubmehl-Prein Chairman of the CSE Dept. and Associate Dean for Research, College of Engineering. He also serves as a Distinguished Visiting Scientist at the Cal Tech/NASA Jet Propulsion Lab.

While at Notre Dame he was part of most government led HPC projects, including HTMT, DIVA, HPCS, and UHPC. He contributed one of the three architectures reported from the seminal 1994 Pasadena Workshop on Petaflops systems (now called "Processing In Memory," with Seymour Cray and Thomas Sterling contributing the others). He led the DARPA Exascale technology study group which in 2008 issued an often-cited report on what would be needed to reach exascale systems. In collaboration with Dr. Jay Brockman this work led to the PIM Lite chip which was designed from the beginning to exist literally next to the sense amps of a memory array.

He is also a Founder of Emu Solutions, Inc., a company dedicated to architecting high performance in-memory systems for data-intensive applications.
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