Timing validation and verification (V&V) assesses software’s end-to-end timing measurements against given budgets. The advent of multicore processors with massive resource sharing reduces the timing for V&V and requires reasoning on worst-case scenarios access delays on contention-prone hardware resources.
While Performance Monitoring Units (PMU) support this finer-grained reasoning, their design has never been a prime consideration in high-performance processors – where automotive-chips PMU implementations descend.
To meet PMUs instrumental importance for timing V&V, researchers from the Barcelona Supercomputing Center advocate for PMUs in automotive chips that explicitly track activities related to worst-case scenario software’s behavior, are recognized as a mandatory high-integrity hardware service.
About Lori Cameron
Lori Cameron is a Senior Writer for the IEEE Computer Society and currently writes regular features for Computer magazine, Computing Edge, and the Computing Now and Magazine Roundup websites. Contact her at firstname.lastname@example.org. Follow her on LinkedIn.