High-Integrity Performance Monitoring Units in Automotive Chips for Reliable Timing V&V

By Lori Cameron
Published 03/30/2018
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As software continues to control more system-critical functions in cars, its timing is becoming an integral element in functional safety, say the authors of “High-Integrity Performance Monitoring Units in Automotive Chips for Reliable Timing V&V.” (Login may be required for full text.)

Timing validation and verification (V&V) assesses software’s end-to-end timing measurements against given budgets. The advent of multicore processors with massive resource sharing reduces the timing for V&V and requires reasoning on worst-case scenarios access delays on contention-prone hardware resources.

While Performance Monitoring Units (PMU) support this finer-grained reasoning, their design has never been a prime consideration in high-performance processors – where automotive-chips PMU implementations descend.

To meet PMUs instrumental importance for timing V&V, researchers from the Barcelona Supercomputing Center advocate for PMUs in automotive chips that explicitly track activities related to worst-case scenario software’s behavior, are recognized as a mandatory high-integrity hardware service.



About Lori Cameron

Lori Cameron is a Senior Writer for the IEEE Computer Society and currently writes regular features for Computer magazine, Computing Edge, and the Computing Now and Magazine Roundup websites. Contact her at l.cameron@computer.org. Follow her on LinkedIn.