Architecting the Future of Energy-Efficient Microprocessors and Reliable Computing Systems

An Interview with Antonio González, Professor of Computer Architecture at Universitat Politècnica de Catalunya (UPC),  2025 B. Ramakrishna Rau Award Recipient. His groundbreaking work in processor microarchitecture, compiler optimization, and energy-aware computing has shaped the evolution of modern computing systems. As the founder of the ARCO research group and former director of the Intel Barcelona Research Center, Dr. González has led transformative research across decades—from speculative execution and clustered architectures to GPU efficiency and cognitive computing. We connected with Dr. González to explore his enduring impact on computer architecture and his vision for sustainable, high-performance systems.

You founded and have led the ARCO research group at UPC since 1989. What have been the most impactful contributions of ARCO in advancing processor microarchitecture and compiler optimization over the past three decades?

Over the past 35 years, our research has evolved in response to the challenges we anticipated for future computer systems. In our early work, we focused on data value and data dependence speculation, developing innovative techniques to predict and break data dependences among instructions. During this initial period, we also put a special focus on improving the architecture of the memory hierarchy. We were among the first to propose cache architectures with specialized modules for different types of locality, register file caches, and register file architectures with heterogeneous banks. Later, our attention shifted to multi-core processors. We developed disruptive techniques to exploit parallelism in multicore processors through the dynamic generation of speculative threads.

By the late 1990's, we anticipated that energy consumption would become the primary bottleneck for future microprocessors, Consequently, we developed a wide range of energy-efficient microarchitectures, such as an adaptive instruction issue queues to reduce its energy consumption. Another major line of our research was clustered microarchitectures, which offer important advantages in both performance—by reducing wire delays—and energy efficiency—by simplifying hardware structures. We proposed multiple novel microprocessor designs and code generation techniques tailored to these architectures.

In the 2000's, we expanded our focus to develop microarchitectural techniques to deal with the increasing susceptibility of transistors to faults caused by environmental effects (e.g., subatomic particle strikes), and device aging. Our group developed highly innovative techniques to counteract these effects, including the Penelope mechanism to mitigate NBTI degradation, and fault tolerant techniques that enable operation at lower voltages to save energy in microprocessors.

In the 2010's, we anticipated the growing prominence of GPUs in computing systems. We began by developing a GPU simulation infrastructure for graphics workloads, which has enabled us to propose microarchitectural innovations that significantly improve their energy-efficiency and performance. More recently, we have extended this work to general-purpose GPU computing, proposing novel core microarchitectures and control-flow management techniques.

In the last decade, we have also worked in the area of cognitive computing systems. We have designed novel microarchitectures for deep neural network accelerators, automatic speech recognition systems, and system-on-chip architectures for autonomous driving.

Across all these efforts, our overarching goal has been to combine high performance with energy efficiency and resilience.

During your tenure as director of the Intel Barcelona Research Center (2002–2014), what were the key areas of collaboration between academia and industry?

At Intel Barcelona Research Center, our mission was to develop innovative microarchitectural enhancements for microprocessors. We worked closely with various Intel divisions to identify challenges and opportunities for improving performance, energy consumption and reliability of next-generation Intel microprocessors.

Simultaneously, we maintained strong academic partnerships, particularly with the Universitat Politècnica de Catalunya (UPC). Intel sponsored a number of open research projects in diverse areas of processor microarchitecture, including power-aware architectures, resilient microarchitectures, memory systems, and multithreaded processors. This collaboration fostered a productive exchange between academic research and industrial innovation, allowing new ideas to be tested and refined in realistic design contexts.

Your recent research has focused on improving GPU energy efficiency for animated graphics and cognitive computing. What architectural strategies have shown the most promise in balancing performance with power constraints in these domains?

Moving forward, it will be imperative that any technique proposed to increase performance must also reduce energy consumption by at least the same proportion. I call this principle the Iron Law of Energy-Efficient Performance. It is derived from the fact that Power = Task_per_unit_of_time x Energy_per_task. Given that for a given product we normally do not want to increase power, increasing performance requires a proportional reduction in the energy needed to execute each task. This is highly challenging, as most conventional performance-boosting techniques (e.g., pipelining, prefetching, speculation) tend to increase rather than decrease energy consumption.

To adhere to this principle, one of our primary strategies has been to eliminate ineffectual computations. This approach typically yields comparable improvements in both performance and energy efficiency. In particular, we have developed a number of techniques that leverage inter-frame coherence — the observation that consecutive frames in animated graphics workloads tend to be very similar. Leveraging this property, we have proposed microarchitectural extensions to identify and skip redundant rendering of entire tiles, primitives (triangles), and fragments, as well as dynamic sampling schemes that reduce precision where visual variation is minimal.

A second major direction to improve GPU performance while adhering to the Iron Law of Energy-Efficient Performance involves improving the effectiveness of the memory hierarchy. We have introduced architectural innovations for tile caches, texture caches, shared last-level caches and main memory systems. These techniques improve performance and also provide dramatic benefits in energy consumption since memory accesses account for a large fraction of GPU energy consumption.

Looking ahead, our research will continue to pursue architectures that deliver sustainable performance growth within the constraints of power and reliability. As emerging workloads in artificial intelligence, autonomous systems, and data analytics become increasingly pervasive, new paradigms of computation will be required to balance efficiency, adaptability, and resilience. At ARCO, we remain committed to advancing this frontier—developing microarchitectures and system designs that not only push the limits of performance but also embody the principles of energy-aware and reliable computing.

Dr. Antonio González's career reflects a deep commitment to advancing computing through innovation, collaboration, and foresight. His contributions—from speculative multithreading to fault-tolerant microarchitectures and GPU optimization—have consistently anticipated the needs of future systems. By championing the Iron Law of Energy-Efficient Performance and pioneering resilient, scalable designs, Dr. González continues to influence how we build computing systems that are not only faster and smarter, but also sustainable and reliable. His legacy in both academia and industry serves as a blueprint for the next generation of computer architects, which is why he is the recipient of the B. Ramakrishna Rau Award.