Norman P. Jouppi

Norman P. Jouppi is a Google Fellow.  He has been the tech lead for Google’s Tensor Processing Units (TPUs) since their inception in 2013.  TPUs currently power the ML capabilities of Google’s applications and are offered publicly in its Cloud.  Before joining Google in 2013 Norm was known for his innovations in computer memory systems, was the principal architect and lead designer of several microprocessors, contributed to the architecture and design of graphics accelerators, and extensively researched telepresence.  His innovations in microprocessor design have been adopted in many high-performance microprocessors. Norm received his Ph.D. in electrical engineering from Stanford University in 1984, and a master of science in electrical engineering from Northwestern University in 1980.  While at Stanford he was one of the principal architects and designers of the MIPS microprocessor, and developed techniques for MOS VLSI timing verification.  He joined HP in 2002 through its merger with Compaq, where he was a Staff Fellow at Compaq’s Western Research Laboratory (formerly DECWRL) in Palo Alto, California.   In 2010 he was named an HP Senior Fellow. From 1984 through 1996 he was a consulting assistant/associate professor in the electrical engineering department at Stanford University where he taught courses in computer architecture, VLSI, and circuit design.  Norm served in the ACM and ACM SIGARCH in various capacities including SIGARCH Chair and ACM Council representative.  He received the SIGARCH Alan D. Berenbaum Distinguished Service Award in 2013. Norm holds more than 125 U.S. patents.  He has published over 125 technical papers, with several best paper awards and two International Symposium on Computer Architecture (ISCA) Influential Paper Awards.  He is the recipient of the 2014 IEEE Harry H. Goode Award and the 2015 ACM/IEEE Eckert-Mauchly Award.  He is a Fellow of the ACM, IEEE, and AAAS, and a member of the National Academy of Engineering.

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