Jiang Xu

Jiang Xu
Professor Jiang Xu

ECE Department
Hong Kong University of Science and Technology
Clear Water Bay, Kowloon
Hong Kong SAR
Phone: +853 2358-5036
Fax: +852 2358-1485
Email: jiang.xu@ust.hk

DVP term expires December 2016

Jiang Xu received his Ph.D. degree from Princeton University. From 2001 to 2002, he worked at Bell Labs, NJ, as a Research Associate and discovered the First Generation Dilemma in platform-based SoC design methodologies. He was a Research Associate at NEC Laboratories America, NJ, from 2003 to 2005 and working on Network-on-Chip designs and implementations. He joined a startup company, Sandbridge Technologies, NY, from 2005 to 2007 and worked on the development and implementation of two generations of NoC-based ultra-low power Multiprocessor Systems-on-Chip for mobile platforms. Dr. Xu established Mobile Computing System Lab and Xilinx-HKUST Joint Lab at the Hong Kong University of Science and Technology. He currently serves as the Area Editor of NoC, SoC, and GPU for ACM Transactions on Embedded Computing Systems and Associate Editor for IEEE Transactions on Very Large Scale Integration (VLSI) Systems. He served on the steering committees, organizing committees, and technical program committees of many international conferences, including ICCAD, CASES, ISVLSI, ICCD, VLSI, EMSOFT, CODES+ISSS, VLSI-SoC, ICESS, RTCSA, NOCS, ASP-DAC, etc. Dr. Xu is an ACM Distinguished Speaker and a Distinguished Visitor of IEEE Computer Society. He authored and coauthored more than 70 book chapters and papers in peer-reviewed journals and international conferences. He and his students received Best Paper Award from IEEE Computer Society Annual Symposium on VLSI in 2009, and Best Poster Award from AMD Technical Forum and Exhibition in 2010. He coauthored a book titled Algorithms, Architecture and System-on-Chip Design for Wireless Applications (Cambridge University Press). His research areas include network-on-chip, multiprocessor system-on-chip, optical interconnect, embedded system, computer architecture, low-power VLSI design, and HW/SW codesign.

More info about Dr. Xu can be found at www.ece.ust.hk/~eexu/.

===Talk 1===


Inter/Intra-Chip Optical Networks: Opportunities and Challenges

Abstract: The performance and energy efficiency of a multi-core system is determined by not only its processor cores but also how efficiently they collaborate with each other. As new applications continuously require more communication bandwidth, metallic interconnects gradually become the bottlenecks of multi-core systems due to their high power consumption, limited bandwidth, and signal integrity issues. Optical interconnects are promising candidates to bring low power, high bandwidth, and low latency to address inter-chip as well as intra-chip communication challenges. Silicon-based photonic devices, such as optical waveguides and microresonators, have been widely demonstrated in CMOS-compatible fabrication processes and can be used to build inter/intra-chip optical networks. This talk will discuss the opportunities and challenges of this emerging technology and present our recent findings.

===Talk 2===


Sensor Network on Chip: A HW-SW Collaborated Method for Resilient MPSoC

Abstract: Multiprocessor system-on-chip (MPSoC) is an attractive platform for embedded applications with growing complexity, because integrating a system or a complex subsystem on a single chip provides better performance and energy efficiency and lower cost per function. As feature sizes and power supply voltages continually decrease, MPSoC is becoming more susceptible to various transient threats, such as soft error and power/ground noise. Traditional solutions introduce large area, power and performance overheads to MPSoC. As the scale and complexity of MPSoC continuously increase, a systematic approach that not only detects reliability threats but also mitigates such threats accordingly at run time could potentially offer better performance, scalability, and flexibility for MPSoC designs. This talk will present a systematic approach, sensor network on chip (SENoC), to collaboratively detect, report, and alleviate run-time transient threats in MPSoC. SENoC not only detects threats and shares related information among processing units, but also plans and coordinates the related reactions. To highlight the details of our idea, SENoC is used and explained in case studies.

===Talk 3===


Network-on-Chip Traffic Patterns Based on Real MPSoC Applications

Abstract: By integrating multiple processing units on a single chip, multiprocessor system-on-chip (MPSoC) can provide higher performance per energy and lower cost per function to applications with burgeoning complexity. The performance of MPSoC is determined not only by the performance of its processing units, but also by how efficiently they collaborate with one another. It is the MPSoC's communication architecture which determines the collaboration efficiency. The on-chip communication architectures of MPSoC are moving from traditional buses and ad-hoc interconnects to more sophisticated network-on-chip (NoC), and have become an active research and developement area in both industry and academic communities. NoC traffic patterns are essential tools for NoC performance assessments and design explorations. The fidelity of NoC traffic patterns has profound influence on NoC studies. Ideally, realistic NoC traffic patterns should capture communication behaviors as well as their temporal and spatial dependencies in real applications. And in addition to communications, they should offer insights into computation tasks and memory usages for comprehensive NoC-based MPSoC research and development. This talk will introduce a set of realistic NoC traffic patterns systematically developed through multidisciplinary collaborations on real MPSoC applications.