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As Moore’s Law slows down, integrating more transistors and system components in a single monolithic die has become challenging and expensive. This has spurred innovations in chiplet integration technologies, including packaging and chiplet-to-chiplet interconnect technologies that can best exploit unique opportunities given by the chiplet technologies. Leading such a technology trend, the industry has already introduced volume products, connecting multiple chiplets with proprietary interconnect technologies. Meanwhile, the need to broaden the participation and ecosystem for chiplet integration technologies has also driven open standards for chiplet interconnect technologies, such as Universal Chiplet Interconnect Express™ (UCIe), High Bandwidth Memory (HBM), and extra short reach (XSR).
This special issue of IEEE Micro seeks articles on broad topics that relate to recent chiplet-to-chiplet interconnect technologies, their impact on future processor, accelerator, and memory architectures, and their novel applications. Topics include, but are not limited to:
For author information and guidelines on submission criteria, please visit IEEE Micro‘s Author Information page. Please submit papers through the ScholarOne system, and be sure to select the special issue name. Manuscripts should not be published or currently submitted for publication elsewhere. Please submit only full papers intended for review, not abstracts, to the ScholarOne portal.
Contact the guest editors at micro6-24@computer.org
Editor-in-Chief Hsien-Hsin Sean Lee
