• IEEE.org
  • IEEE CS Standards
  • Career Center
  • About Us
  • Subscribe to Newsletter

0

IEEE
CS Logo
  • MEMBERSHIP
  • CONFERENCES
  • PUBLICATIONS
  • EDUCATION & CAREER
  • VOLUNTEER
  • ABOUT
  • Join Us
CS Logo

0

IEEE Computer Society Logo
Sign up for our newsletter
IEEE COMPUTER SOCIETY
About UsBoard of GovernorsNewslettersPress RoomIEEE Support CenterContact Us
COMPUTING RESOURCES
Career CenterCourses & CertificationsWebinarsPodcastsTech NewsMembership
BUSINESS SOLUTIONS
Corporate PartnershipsConference Sponsorships & ExhibitsAdvertisingRecruitingDigital Library Institutional Subscriptions
DIGITAL LIBRARY
MagazinesJournalsConference ProceedingsVideo LibraryLibrarian Resources
COMMUNITY RESOURCES
GovernanceConference OrganizersAuthorsChaptersCommunities
POLICIES
PrivacyAccessibility StatementIEEE Nondiscrimination PolicyIEEE Ethics ReportingXML Sitemap

Copyright 2025 IEEE - All rights reserved. A public charity, IEEE is the world’s largest technical professional organization dedicated to advancing technology for the benefit of humanity.

FacebookTwitterLinkedInInstagramYoutube
  • Home
  • /Digital Library
  • /Magazines
  • /Mi
  • Home
  • / ...
  • /Magazines
  • /Mi

CLOSED Call for Papers: Special Issue on Compiling for Accelerators

Hardware accelerators are rapidly becoming a central architectural feature to improve computation power performance. CPU ISA extensions, custom-designed engines, and FPGA-based systems have been proposed as acceleration architectures to improve program execution in scientific, machine-learning, database, and other application domains. Although much effort has been devoted to the design of accelerators, there is still a large gap of knowledge on how to make effective use of and compile for such architectures. As history has already taught us, having a great architecture is only half of the path to designing an efficient computing machine. Understanding the techniques required for quality code generation is central to the long-term establishment of an acceleration-based architectural paradigm.

This special issue of IEEE Micro will explore academic and industrial research on topics that relate to compiling for accelerators. Topics of interest include, but are not limited to:

  • Compiling for CPU ISA extensions
  • Code generation for neural processing units
  • Compiling for neural network training
  • Programming linear algebra engines
  • Code generation and programming for database accelerators
  • Processor-accelerator interface design and programmability
  • Compiling for energy efficiency
  • Pattern matching and code replacement for acceleration instructions
  • High-level synthesis design of custom engines
  • DSL and parallel programming models for accelerators
  • Compiler intermediate representation (IR) and optimization techniques for accelerators
  • Programming FPGAs for custom computing engines
  • Tools and libraries to support code generation for accelerators

Important Dates

Submission Deadline: December 22, 2021

Initial notifications: March 15, 2022

Revised papers due: April 8, 2022

Final notifications: May 13, 2022

Final versions due: May 31, 2022

Publication: July/August 2022

Submission Guidelines

Please see the Author Information page and the Magazine Peer Review page for more information. Please submit electronically through ScholarOne Manuscripts, selecting this special-issue option.

For the manuscript submission, acceptable file formats include Microsoft Word (*) and PDF. Manuscripts should not exceed 5,000 words including references, with each average-size figure counting as 250 words toward this limit. Please include all figures and tables, as well as a cover page with author contact information (name, postal address, phone, fax, and email address) and a 200-word abstract. Submitted manuscripts must not have been previously published or currently submitted for publication elsewhere, and all manuscripts must be cleared for publication. All previously published papers must have at least 30% new content compared to any conference (or other) publication. Accepted articles will be edited for structure, style, clarity, and readability.

Questions?

Contact guest editors Guido Araujo and Lucas Wanner at micro4-22@computer.org, or the editor-in-chief Lizy John at ljohn@ece.utexas.edu.

Please direct ScholarOne-related questions to the IEEE Micro magazine assistant at micro-ma@computer.org.

LATEST NEWS
IEEE Uganda Section: Tackling Climate Change and Food Security Through AI and IoT
IEEE Uganda Section: Tackling Climate Change and Food Security Through AI and IoT
Blockchain Service Capability Evaluation (IEEE Std 3230.03-2025)
Blockchain Service Capability Evaluation (IEEE Std 3230.03-2025)
Autonomous Observability: AI Agents That Debug AI
Autonomous Observability: AI Agents That Debug AI
Disaggregating LLM Infrastructure: Solving the Hidden Bottleneck in AI Inference
Disaggregating LLM Infrastructure: Solving the Hidden Bottleneck in AI Inference
Copilot Ergonomics: UI Patterns that Reduce Cognitive Load
Copilot Ergonomics: UI Patterns that Reduce Cognitive Load
Read Next

IEEE Uganda Section: Tackling Climate Change and Food Security Through AI and IoT

Blockchain Service Capability Evaluation (IEEE Std 3230.03-2025)

Autonomous Observability: AI Agents That Debug AI

Disaggregating LLM Infrastructure: Solving the Hidden Bottleneck in AI Inference

Copilot Ergonomics: UI Patterns that Reduce Cognitive Load

The Myth of AI Neutrality in Search Algorithms

Gen AI and LLMs: Rebuilding Trust in a Synthetic Information Age

How AI Is Transforming Fraud Detection in Financial Transactions

Get the latest news and technology trends for computing professionals with ComputingEdge
Sign up for our newsletter