CLOSED Call for Papers: IEEE Micro Special Issue on Monolithic 3D Architectures
Submissions due: CLOSED
Publication date: November/December 2019
Going vertical is a promising option to continue density scaling beyond traditional transistor scaling. The initial wave of three-dimensional architectures have focused on connecting stacked chip layers by through silicon vias (TSVs). However, the challenges with dimensional scaling of TSVs has limited the degree of interaction across different layers. New monolithic 3D integration technologies have enabled nanoscale interconnections, orders of magnitude smaller than TSVs, providing massive vertical connectivity. This data connectivity provides new opportunities for micro-architectural and architectural innovations to reduce the energy associated with data movement and enhance the performance of applications that operate on a massive amount of data. The integration of heterogeneous technologies within the same chip can also drive innovations in algorithms and system realizations.
This special issue of IEEE Micro will explore academic and industrial research on all topics related to monolithic 3D architectures. Topics include, but are not limited to:
Survey and tutorial on monolithic process technologies
Application-specific customization leveraging monolithic 3D integration
Micro-architectural innovations using monolithic 3D
In-memory computational fabrics leveraging 3D interconnects
Thermal and power analysis of monolithic systems
3D reconfigurable architectures and FPGA designs
Heterogeneous systems on a chip
Network on chip fabrics for monolithic 3D technologies
Processor design using monolithic 3D
Benchmarking of processor architectures using different 3D technologies
