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Submissions due: CLOSED
Publication date: November/December 2019
Going vertical is a promising option to continue density scaling beyond traditional transistor scaling. The initial wave of three-dimensional architectures have focused on connecting stacked chip layers by through silicon vias (TSVs). However, the challenges with dimensional scaling of TSVs has limited the degree of interaction across different layers. New monolithic 3D integration technologies have enabled nanoscale interconnections, orders of magnitude smaller than TSVs, providing massive vertical connectivity. This data connectivity provides new opportunities for micro-architectural and architectural innovations to reduce the energy associated with data movement and enhance the performance of applications that operate on a massive amount of data. The integration of heterogeneous technologies within the same chip can also drive innovations in algorithms and system realizations.
This special issue of IEEE Micro will explore academic and industrial research on all topics related to monolithic 3D architectures. Topics include, but are not limited to:
Submissions due: June 19, 2019
Please see the Author Information page and the peer review page for more information. Please submit electronically through ScholarOne Manuscripts, selecting this special-issue option.
Contact the guest editor, Vijay Narayanan (vijay@cse.psu.edu) or the editor-in-chief, Lizy John (ljohn@ece.utexas.edu).
