Closed Call for Papers: Special Issue on Emerging System Interconnects

Share this on:
Submissions Due: 14 September 2022

Important Dates

  • Submissions Due: 14 September 2022
  • Initial Notifications: 16 November 2022
  • Revision Due: 21 December 2022
  • Final Notifications: 25 January 2023
  • Final Version Due: 8 February 2023

Publication: March/April 2023

The Moore’s Law scaling has approached the fundamental limit of physics and its end is in sight. Consequently, integrating more transistors and system components in a single monolithic die has become cost-ineffective and inefficient. This has led to two innovations in (1) integration and packaging technologies that integrate multiple system components in separate dies into a single chip package; (2) heterogeneous computing, which allows us to continue to scale performance and energy efficiency with various accelerators. In parallel, with proliferation of cloud computing enabled by large-scale datacenters, efficient use of compute, memory and storage resources through disaggregation has become very important for cost-effective operation of the datacenters. These have called for system interconnect technologies, efficiently connecting dies in a chip package and chips in a system board and across boards to cost-effectively build a scalable system. This special issue of IEEE Micro will explore academic and industrial research on topics that relate to recent emerging interconnect technologies, their impact on future computer architecture, and their novel applications. Topics include, but are not limited to:

  • Cache coherent interconnects for I/O and compute devices (e.g., CXL, CCIX, …)
  • High-speed interconnects for memory expansion and disaggregation
  • In-package die-to-die interconnects for chiplet integration (e.g., UCIe, BoW, etc.)
  • NVMe over Fabric
  • Emerging interconnect technologies (e.g., optics, wireless, etc.) for memory and accelerator interconnect systems
  • Architecture/system implications from such interconnect (e.g., impact on memory hierarchy, xPU architecture, etc.) 
  • Performance characterization and/or novel applications of the emerging memory-centric interconnect technologies

Submission Guidelines

For author information and guidelines on submission criteria, please visit IEEE Micro‘s Author Information page. Please submit papers through the ScholarOne system, and be sure to select the special-issue name. Manuscripts should not be published or currently submitted for publication elsewhere. Please submit only full papers intended for review, not abstracts, to the ScholarOne portal.


Please contact the guest editors at

Guest Editors

  • Dr. Nam Sung Kim
  • Dr. John Kim