A 1993 highly integrated graphics chip designed with a system focus
In 1993, facing heavy competition from Sun, HP set the design goal for its new 32-bit HP 9000/712 workstation to reach performance levels of 1992-era workstations and servers at a fraction of their fabrication costs. Their target was the earlier generation HP 9000/735. To accomplish that HP employed VLSI technologies for the processor components, which were state of the art at the time.
What they came up with was the heart of the system: the famous PA-RISC CPU, and its equally impressive coprocessor was the Artist chip to replace the CRX window accelerator add-in board (AIB). That board marked the beginning of standardized graphics hardware architecture for window system acceleration.
The CRX marked the beginning of a standardized graphics hardware architecture for window system acceleration. That architecture was chosen for its simplicity of implementation and for the clean model it presented to the software driver developers. One of HP’s fundamental design decisions was to accelerate key primitives only—a RISC approach. Many earlier controllers chose to accelerate a large gamut of graphical operations such as ellipses, arithmetic pixel operations, and so on. Graphics subsystems designed with these controllers were typically expensive and exhibited only moderate window system performance. In the CRX and subsequent accelerators, including the Model 712’s graphics chip, HP decided to accelerate a carefully chosen smaller set of primitives, which are described in the following sections.
When the engineers at HP approached the problem of reducing costs, there were three major areas the chip was intended to address (in order of priority):
- Fast 2-D GUI
- Digital video decompression support—both locally and over LAN/WAN
- Efficient 3-D graphics
Additionally, the designers included
- Vector, rectangle, framebuffer bitBLT, text cursor hardware
- Bit/pixel framebuffer access mode, VRAM block write
- Boolean raster operations
- Two look-up tables to reduce palette conflict.
The Artist chip combined a GUI accelerator, a frame buffer controller (32-bits wide), two look up tables LUTs), video timing, cursor control and an integrated LUT-DAC. The chip was capable of supporting 1 or 2 Mbytes of VRAM and provided 8 bits up to its highest resolution of 1280 × 1024 at 72 Hz non-interlaced refresh. A ninth-bit controlled selection of one of the two LUT-DACs. The chip also included a built-in programmable PLL that eliminated the need of a timing crystal.
The design balanced the CPU’s strengths with those of the graphics controller and did the video compression and decompression on the CPU while performing color space conversion and compression/decompression on the Artist chip.
Figure 1: Balanced compression/decompression with CPU and Artist chop (Source HP)
HP also developed a proprietary color compression algorithm, that could squeeze 24-bit color to 8 bits while retaining the look of 24-bit color.
The performance of the Artist chip was impressive for the times:
- Large rectangle fill 850 Mpixels/second
- Vectors/second (10-pixel random) 21 M/second
- 10 x 10 rectangles 1.7M/second
- Text (6 x 13 characters/second) 1M
- 3-D transformed vectors/second >1M
- Frame buffer bitBLT (unaligned pixels/second) 47 M
The CPU handled transformations and clipping as well as lighting, z-buffering and pixel color interpolation for polygons. The Artist chip took care of vector rasterizing and color compression into the frame buffer. The chip 70 ns VRAMs and got a 37.5 ns page mode speed, while utilizing the features of the VRAM for plane mask, extended data out and block copy. As a result, the chip could deliver 850 Mpixels/second for constant-color objects.
Figure 2: HP’s Artist chip block diagram (Source HP)
The chip had 525,000 transistors, built in 0.8 micron 3-layer (aluminum) HP CMOS26B process. The die size was 9.7 x 12.1 mm and HP packaged it in 208-pin metal QFP or 240 MQFP with flat-panel driver output. The chip had a 40-80 MHz GUI/RAM clock and generated a 25-135 MHz video output — and it only used 3.5 W worst case.
As mentioned, low cost was the primary objective for the graphics chip design. As a measure of HP’s success, the manufacturing cost for the Model 712 graphics subsystem was 1/3 the cost of the original CRX graphics subsystem. In addition, the entry-level 1024-by-768-pixel version of the graphics chip costs five times less than the CRX subsystem.
These cost reductions were achieved primarily through an aggressive amount of integration. The graphics chip represents the culmination of a series of optimizations of the CRX family, combining almost the entire GUI accelerator onto a single chip. The only major function not integrated was the frame buffer.
The HP Artist chip was one of the first to employ software programmable resolutions. One of the problems with previous workstation graphics subsystems was that they operated at a fixed video resolution and refresh rate. That posed problems in configuring systems at the factory and during customer upgrades.
The Artist graphics chip incorporates an advanced digital frequency synthesizer that generates the clocks necessary for the video subsystem. The synthesizer, which was based on a HP proprietary digital phase-locked loop technology, allowed software configurability of the resolution and frequency of the video signal. Thus, alternate monitors could be connected without changing any video hardware. The originally supported configurations included:
- 640 by 480 pixels 60 Hz, standard VESA timing
- 800 by 600 pixels 60 Hz
- 1024 by 1024 pixels 75 Hz and flat panel
- 1280 by 1024 pixels 72 Hz.
As new monitor timings appeared, the graphics chip could simply be reprogrammed with the parameters associated with the new monitor.
HP created the graphics chip with the philosophies of system- level-optimized design and optimal use of technology. That enabled them to meet their goals of very low manufacturing cost, good performance at their cost point, architectural compatibility, and introduction of some important new functionality. The Artist chip was a breakthrough product for HP and served them well for many years.
In the 1980s and early 1990s, semiconductors were laid out on large backlit plotter tables. The layout engineers used to put a signature, or a symbol, a cartoon, or a picture in the pattern somewhere. It was done for three reasons, A. to sign a work of art, B. for copyright protection, and C. because they could (it was difficult). Later when the layout was done on a computer, many designers carry on the tradition.
Image courtesy Florida State University’s Silicon Zoo project
The above micrograph is a logo that was concealed on an early 90s HP chip. The same chip also featured 20 designers’ initials as well as the message “If you can read this…. you are too damn close!”