Jyotika Athavale is a Senior Technical Leader and Experienced Principal Engineer at Intel Corporation. She is a recognized industry expert with in-depth technical knowledge of platform technologies and architectures for Safety Critical Systems, with a focus on radiation effects modeling for soft errors performance. Jyotika is currently focused on pathfinding research on incubation technologies and strategies for future IOT platforms. Based in Chandler, Arizona, her 24 years of industry career experience in the semiconductor and EDA industry has spanned technical leadership positions as well as people management roles.
A frequent conference speaker at international leading conferences, Jyotika actively contributes to these IEEE events via papers, invited talks and panel presentations. She also serves on the program committee of the DATE and IQPC ISO26262 for Semiconductors conferences. She has authored several IEEE publications and is actively engaged in IEEE international standards activities including the IEEE P2851 standard on safety analysis interoperability, for which she serves in the position of Secretary. She is also a member of the IEEE P2846 standard WG, the IEEE Design Automation Standards Committee and participates in SAE standards groups as well as the Partnership on AI Industry Consortium.
Jyotika is a core team member of the IEEE Computer Society Special Technical Community for Reliable, Safe, Secure and Time Deterministic Intelligent Systems and is also a member of the IEEE Computer Society Technical Committee on Dependable Computing and Fault Tolerance. She is a professional member of the Society of Women Engineers and IEEE Women in Engineering. Jyotika is an active mentor to IEEE Student Members in IEEE Region 6. She actively promotes research programs for universities in collaboration with NASA and CERN in an associate partner role for RADMEP Technologies and Supervisory board member of RADSAGA. She holds a master’s degree in electrical engineering from Iowa State University.
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