Shiyan Hu

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Professor Shiyan Hu
Department of Electrical and Computer Engineering
EERC 518
Michigan Technological University Houghton,
1400 Townsend Drive, MI, 49931, USA
Phone: (906)487-2941
Fax: (906)487-2949

DVP term expires December 2017
Professor Shiyan Hu received his Ph.D. in Computer Engineering from Texas A&M University in 2008. He is currently an Associate Professor in the Department of Electrical and Computer Engineering at Michigan Technological University, where he is Director of the Michigan Tech Cyber-Physical System Research Group, Co-Director of Michigan Tech Institute of Computing and Cybersystems, and Director of the Michigan Tech VLSI CAD Research Lab. He was a Visiting Professor at IBM Research (Austin) during Summer 2010, and he is a Visiting Associate Professor at Stanford University starting 08/2015.
Prof. Hu’s research interests include Computer-Aided Design of VLSI Circuits, Embedded Systems, Cyber-Physical Systems and Cybersecurity, where he has published about 100 refereed papers, including 20+ in the premier IEEE Transactions. His microfluidic biochip physical design paper was featured in the Front Cover of the premier IEEE Transactions on Nanobioscience in March 2014, and his papers have been nominated for IEEE/ACM ICCAD William J. McCalla Best Paper Award in 2009 and IBM Pat Goldberg Best Paper Award in 2008 and 2010.
Prof. Hu is the Founding Chair for IEEE Technical Committee on Cybernetics for Cyber-Physical Systems. He is an ACM Distinguished Speaker, an IEEE Computer Society Distinguished Visitor, a recipient of ACM SIGDA Richard Newton DAC Scholarship (as the faculty advisor), a recipient of Faculty Invitation Fellowship from Japan Society for the Promotion of Science (JSPS), and a recipient of the National Science Foundation (NSF) CAREER Award. He is an Associate Editor/Guest Editor for 5 IEEE/ACM Transactions including IEEE Transactions on Circuits and Systems, IEEE Transactions on Computers, IEEE Transactions on CAD, IEEE Transactions on Industrial Informatics and ACM Transactions on Embedded Computing Systems. He has served as General Chair, Technical Program Committee (TPC) Chair, TPC Subcommittee Chair, Session Chair, and TPC Member for various conferences for more than 70 times, which include the TPC Subcommittee Chair for DAC 2014, 2015 and ICCAD 2011. He is a Senior Member of IEEE.
Prof. Hu’s research has been highlighted in various public media such as CBS, IEEE Spectrum, Communications of ACM, Science Daily, PC World, Daily News and Biotech Daily. His ultra fast slew buffering technique has been widely deployed in industry. As an example, it became a default option in the IBM physical design flow used for designing over 50 microprocessors and ASIC chips including IBM flagship chips POWER 7 and 8. He was among 62 researchers invited from the European Union and the United States to attend the EU-US Frontiers of Engineering Symposium of National Academy of Engineering in 2014.


Smart Home Cybersecurity: Threat and Defense in a Cyber-Physical System

The massive deployment of advanced metering infrastructure and home energy management system has mandated a transformative shift of the classical grid into a more reliable and secure grid. Smart home is critical in this infrastructure as it controls the end use components of a grid. Despite its importance, such a system is vulnerable to various cyberattacks such as energy theft and pricing hack. In this talk, I will describe several of our recent works on smart home cyberthreat analysis and defense technology development. I will first show that due to the interdependence between utility pricing and customer energy load, a cyberattacker could tamper smart meters for electricity bill manipulation and energy load unbalancing, and similarly energy theft could potentially disturb the power system. I will then discuss some advanced control theoretic and algorithmic techniques developed in my group to defend against those cyberattacks, including partially observable Markov decision process (POMDP) based detection and cross entropy optimization based Feeder Remote Terminal Unit (FRTU) deployment optimization. I will conclude the talk with some of the future research directions on this topic.


Nanoscale Interconnect Optimizations for Emerging Technologies

As the VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Interconnect synthesis which includes buffer insertion and layer assignment is indispensable in the physical synthesis flow. In this talk, I will first introduce the classical dynamic programming based buffer insertion and layer assignment techniques. I will then highlight our recent work on developing a new provably good algorithm for the timing driven minimum cost buffer insertion problem. This NP-hard problem has been studied for over a decade but there is little success in designing efficient approximations. Our algorithm is the first fully polynomial time approximation scheme which can approximate the optimal solution within a factor of 1+e running in O(m2n2b/e3+n3b2/e) time for any 0<e<1.  I will then show how this algorithm can be extended to handle layer assignment. Finally, I will briefly describe our recently developed buffer insertion technique for the carbon nanotube interconnect based IC design, which is the first buffering technique in this emerging research area.