Anirban Sengupta
2019-2021 Distinguished Speaker

Biography

Dr. Anirban Sengupta is an Associate Professor in Computer Science and Engineering at the Indian Institute of Technology (I.I.T) Indore He holds a Ph.D. & M.A.Sc in Electrical and Computer Engineering from Ryerson University, Toronto (Canada) and is a registered Professional Engineer of Ontario (P.Eng.).

He is a Fellow of IET and Fellow of British Computer Society (BCS), UK. He is IEEE Distinguished Lecturer of IEEE Consumer Electronics Society and IEEE Distinguished Visitor of IEEE Computer Society. He is Chair of IEEE Computer Society TCVLSI and Founder & Chair of IEEE Consumer Electronics Society Chapter – Bombay Section. He has been an active researcher in the emerging areas of Hardware Security, IP Core Protection and Digital Rights Management for Electronics Devices. He has 190 publications and patents. He is an author of a Book from IET on “IP Core Protection and Hardware-Assisted Security for Consumer Electronics”  released in 2019. He is also Deputy Editor-in-Chief of IET Computers and Digital Techniques, Editor-in-Chief of IEEE VLSI Circuits and Systems Letter, Associate Editor of IEEE Transactions on VLSI Systems, IEEE Transactions on Consumer Electronics and IEEE Transactions on Aerospace and Electronic Systems.

He currently serves/served in several editorial positions as Senior Editor, Associate Editor, Editor and Guest Editor of several IEEE Transactions/Journals, IET and Elsevier Journals including IEEE Transactions on Aerospace and Electronic Systems (TAES), IEEE Transactions on VLSI Systems, IEEE Transactions on Consumer Electronics, IEEE Access Journal, IET Journal on Computer & Digital Techniques, IEEE Consumer Electronics, IEEE Canadian Journal of Electrical and Computer Engineering, IEEE VLSI Circuits & Systems Letter and Elsevier Microelectronics Journal. He further serves as Guest Editor of IEEE Transactions on VLSI Systems, IET Computers and Digital Techniques and . He is the General/Conference Chair of 37th IEEE International Symposium on Consumer Electronics (ICCE) 2019, Las Vegas and Technical Program Chair of 36th IEEE International Conference on Consumer Electronics (ICCE) 2018 in Las Vegas,. More than a dozen of his IEEE publications have appeared in ‘Top 50 Most Popular Articles’ with few in ‘Top 5 Most Popular Articles’ from IEEE Periodicals. His patents have been cited in industry patents of IBM Corporation, Siemens Corporation, Qualcomm, Amazon Technologies, Siemens (Germany), Mathworks Inc, Ryerson University and STC University of Mexico multiple times.

He was awarded the “Outstanding Associate Editor” Award from IEEE TCVLSI Letter Editorial Board, IEEE Computer Society in September 2017. He was inducted into the Executive Committee of IEEE Computer Society Technical Committee on VLSI in October 2017. His works were awarded the “IEEE Consumer Electronics Society Best Research Paper Award 2019” in IEEE CE Society’s Flagship Conference—37th IEEE International Conference on Consumer Electronics (ICCE) 2019, Las Vegas (USA), the “IEEE Computer Society Technical Committee on VLSI—Best Paper Award” in IEEE International Symposium on Nanoelectronic and Information Systems (iNIS 2017) and the “IETE Best Research Award” by IETE Sub-Center in 2018.

Indian Institute of Technology (I.I.T) Indore

Phone:

Email: asengupt@iiti.ac.in

Website: http://www.anirban-sengupta.com/

DVP term expires December 2021


Presentations

Anti-Piracy Aware IP Chipset Design for Integrated Circuits

Intellectual property (IP) chipsets are indispensable components of consumer electronics (CE) products such as set-top boxes, digital TVs, DVDs, tablets, digital cameras, audio-video receivers etc. IP chipsets represent several man-years of investment, research and development through expensive infrastructure. Watermarking in IP chipsets for protection of CE devices against false claim of ownership, piracy and counterfeit has been proved as a promising solution. However, the design process of a watermarked (anti-piracy aware) IP chipset is complex, and no published work exists in the literature to introduce a formal design methodology. This paper presents a formal design approach for anti-piracy aware IP chipsets for CE devices. Using robust multi-variable signature encoding methodology, decoded watermarking constraints are embedded into the formal architectural synthesis design steps of an IP chipset. Each step of the IP chipset design will be lucidly introduced with the aid of a real life benchmark from the domain of multimedia and digital signal processing.

 

Protection of IP-Core Designs for Integrated Circuits

The current design era of consumer electronics is reliant on global IC supply chains. To maximize design productivity and minimize design time, the use of intellectual property (IP) cores, often supplied by a third party vendor, has become standard practice in the industry. However, there are increasing threats to security, and growing piracy issues that threaten global supply chains as system-on-chip design becomes increasingly commoditised. Consequently, the requirements for protection of IP-core designs and the know-how they represent has become of importance to industry. This topic provides an insight into this challenge faced by many CE manufacturers and an overview of current and past methodologies. The pros and cons of each approach and some practical case studies will help understand this challenge. Some consideration is also given to the potential future evolution of IP protection.

 

Hardware Security of Integrated Circuits: Threat Models and Defense against IP Trojans and IP Piracy

This topic will delve deep into the threat models and defense mechanisms against hardware Trojans and IP piracy. This topic discusses the hardware security of consumer electronics (CE) devices, focusing primarily on threat models and defense mechanisms against two major attacks: hardware Trojans and IP piracy. Further, other hardware-related IP attacks on CE design will be discussed along with its security mechanism. Design for security will be emphasized for CE community designers and practitioners who focus on IP core security.

Presentations

  • Anti-Piracy Aware IP Chipset Design for Integrated Circuits
  • Protection of IP-Core Designs for Integrated Circuits
  • Hardware Security of Integrated Circuits: Threat Models and Defense against IP Trojans and IP Piracy

Read the abstracts for each of these presentations