Dr. Anirban Sengupta is an Associate Professor in Computer Science and Engineering at Indian Institute of Technology (I.I.T) Indore, where he directs the research lab on ‘CAD for Consumer Electronics Hardware Device Security & Reliability’. He is an elected Fellow of IET and Fellow of British Computer Society (FBCS), UK. He holds a Ph.D. & M.A.Sc in Electrical & Computer Engineering from Ryerson University, Toronto (Canada) and is a registered Professional Engineer of Ontario (P.Eng.). He has been an active researcher in the emerging areas of ‘Hardware Security’, ‘IP Core Protection’ and ‘Digital Rights Management for Electronics Devices’. He has been awarded prestigious IEEE Distinguished Lecturer by IEEE Consumer Electronics Society in 2017 and IEEE Distinguished Visitor by IEEE Computer Society in 2019. He is Ex-Officio member of Board of Governors of IEEE Consumer Electronics Society. He has featured in ‘Researcher Spotlight’ of prestigious ACM Special Interest Group on Design Automation (SIGDA) Newsletter for his contributions on hardware security.
He has over 230 Publications & Patents. He is an author of two books from IET on “IP Core Protection and Hardware-Assisted Security for Consumer Electronics” and “Frontiers in Securing IP Cores – Forensic detective control and obfuscation techniques” published in 2019 and 2020 respectively from United Kingdom. He is also author of an edited book from Springer on “VLSI Design and Test” published in 2020. He is currently Deputy Editor-in-Chief of IET Computers and Digital Techniques Journal that has a publishing history of over 40 years and Editor-in-Chief of IEEE VLSI Circuits & Systems Letter of IEEE Computer Society TCVLSI. He is currently the Chairman of IEEE Computer Society TCVLSI. He currently serves/served in several Editorial positions as Senior Editor, Associate Editor, Editor and Guest Editor of several IEEE Transactions/Journals, IET and Elsevier Journals including IEEE Transactions on Aerospace and Electronic Systems (TAES), IEEE Transactions on VLSI Systems, IEEE Transactions on Consumer Electronics, IEEE Access Journal, IEEE Letters of Computer Society, IET Journal on Computer & Digital Techniques, IEEE Consumer Electronics Magazine, IEEE Canadian Journal of Electrical and Computer Engineering, IEEE VLSI Circuits & Systems Letter and Elsevier Microelectronics Journal. He further serves as Guest Editor of IEEE Transactions on VLSI Systems, IEEE Access and IET Computers & Digital Techniques. He was the General/Conference Chair of 37th IEEE International Symposium on Consumer Electronics (ICCE) 2019, Las Vegas, General/Conference Chair of 23rd International Symposium On VLSI Design And Test – VDAT and Technical Program Chairs of 36th IEEE International Conference on Consumer Electronics (ICCE) 2018 in Las Vegas, 10th IEEE International Conference on Consumer Electronics (ICCE) – Berlin 2020, 9th IEEE International Conference on Consumer Electronics (ICCE) – Berlin 2019, 15th IEEE International Conference on Information Technology (ICIT) 2016, 3rd IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) 2017. Further he has served in Executive Committee of IEEE International Conference on Consumer Electronics (ICCE) – Berlin, IEEE International Conference on Consumer Electronics (ICCE) – Las Vegas as well as International Advisor of IEEE International Conference on Consumer Electronics (ICCE) – Las Vegas.
More than a dozen of his IEEE publications have appeared in ‘Top 50 Most Popular Articles’ with few in ‘Top 5 Most Popular Articles’ from IEEE Periodicals. His patents have been cited in industry patents of IBM Corporation, Siemens Corporation, Qualcomm, Amazon Technologies, Siemens (Germany), Mathworks Inc, Ryerson University and STC University of Mexico multiple times. His professional works have received wide media coverage nationally and internationally such as in IET International News (UK), Times of India, Central Chronicle, DBPOST News, Free Press Journal, Dainik Bhaskar etc. He has supervised more than 35 candidates including several graduated Ph.D. candidates, Research Assistants, Associates, B.Tech’s all of whom are/were placed in academia and industry. He has successfully commissioned special issues in IEEE TVLSI, IEEE TCAD, IET CDT, IEEE Access as well as IEEE CEM. He has been awarded highest rating ‘Excellent’ by Department of Science & Technology (DST) based on the performance in funded project in 2017. His ideas have been awarded funding from Department of Science & Technology (DST), Council of Scientific and Industrial Research (CSIR) and Department of Electronics & IT (DEITY). Complete details available at: http://www.anirban-sengupta.com/index.php
Indian Institute of Technology (I.I.T) Indore
DVP term expires December 2021
Anti-Piracy Aware IP Chipset Design for Integrated Circuits
Intellectual property (IP) chipsets are indispensable components of consumer electronics (CE) products such as set-top boxes, digital TVs, DVDs, tablets, digital cameras, audio-video receivers etc. IP chipsets represent several man-years of investment, research and development through expensive infrastructure. Watermarking in IP chipsets for protection of CE devices against false claim of ownership, piracy and counterfeit has been proved as a promising solution. However, the design process of a watermarked (anti-piracy aware) IP chipset is complex, and no published work exists in the literature to introduce a formal design methodology. This paper presents a formal design approach for anti-piracy aware IP chipsets for CE devices. Using robust multi-variable signature encoding methodology, decoded watermarking constraints are embedded into the formal architectural synthesis design steps of an IP chipset. Each step of the IP chipset design will be lucidly introduced with the aid of a real life benchmark from the domain of multimedia and digital signal processing.
Protection of IP-Core Designs for Integrated Circuits
The current design era of consumer electronics is reliant on global IC supply chains. To maximize design productivity and minimize design time, the use of intellectual property (IP) cores, often supplied by a third party vendor, has become standard practice in the industry. However, there are increasing threats to security, and growing piracy issues that threaten global supply chains as system-on-chip design becomes increasingly commoditised. Consequently, the requirements for protection of IP-core designs and the know-how they represent has become of importance to industry. This topic provides an insight into this challenge faced by many CE manufacturers and an overview of current and past methodologies. The pros and cons of each approach and some practical case studies will help understand this challenge. Some consideration is also given to the potential future evolution of IP protection.
Hardware Security of Integrated Circuits: Threat Models and Defense against IP Trojans and IP Piracy
This topic will delve deep into the threat models and defense mechanisms against hardware Trojans and IP piracy. This topic discusses the hardware security of consumer electronics (CE) devices, focusing primarily on threat models and defense mechanisms against two major attacks: hardware Trojans and IP piracy. Further, other hardware-related IP attacks on CE design will be discussed along with its security mechanism. Design for security will be emphasized for CE community designers and practitioners who focus on IP core security.
- Anti-Piracy Aware IP Chipset Design for Integrated Circuits
- Protection of IP-Core Designs for Integrated Circuits
- Hardware Security of Integrated Circuits: Threat Models and Defense against IP Trojans and IP Piracy