CLOSED Call for Papers: Special Topic on Monolithic 3D Integration for Energy-Efficient Computing

Special Topic on Monolithic 3D Integration for Energy-Efficient Computing
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Submissions Due: 15 April 2021


IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

Special Topic on Monolithic 3D Integration for Energy-Efficient Computing

Guest Editor

Shimeng Yu, Georgia Institute of Technology,


Azad Naeemi, Georgia Institute of Technology,

Aims and Scope

As the traditional 2D scaling is approaching its physical limit, there is a great motivation to explore the 3rd dimension for future integrated circuit design. The Memory industry has already adopted monolithic 3D integration (e.g. in 176-layer 3D NAND Flash), while the 3D vertical integration structure of logic transistors (e.g. 3D stacked nanosheets, NMOS on top of PMOS) is emerging for sub-3 nm logic nodes. The other trend is to stack the embedded non-volatile memories (e.g. RRAM, PCM, MRAM, FeFET) on top of CMOS using the back-end-of-line (BEOL) processing. Taking one step further, integration of multiple tiers of active transistors with embedded memories is expected to offer significant improvements of the throughput and energy efficiency thanks to the massive connectivity between logic and memories. Besides the technological breakthroughs, circuit design automation methodologies become key enablers to optimize the tier partitioning in monolithic 3D architectures. In addition, heat dissipation should be taken care of by accurate thermal modeling in these monolithic 3D architectures. New heat spreading materials and advanced embedded cooling techniques are also important.

In the context of this call for papers, monolithic 3D integration is defined as multi-tier integration of logic transistors and/or memory devices using fine-pitch vias (<500nm), as distinguished from the conventional through silicon via (TSV) approach. We do not limit the scope of the monolithic 3D integration to the sequential processing, but also welcome other 3D stacking methods including the layer transfer and die stacking as long as the inter-via density is high (>1E6/mm2).

This special issue of the IEEE Journal on Exploratory Computational Devices and Circuits (JXCDC) aims to call for the recent research advances in the area of the monolithic 3D integration spanning from materials/devices towards circuits/ architectures for energy-efficient computing. Papers on cross-layer interaction and co-optimization are encouraged.

Topics of Interests

Prospective authors are invited to submit original works and/or extended works based on conference presentations on various aspects of monolithic 3D integration technologies. Topics of special interest include but are not limited to:

  • Monolithic 3D transistors and their circuit and system implications (e.g. complementary FET, NMOS on top of PMOS)
  • Back-end-of-line compatible transistors (e.g. based on semiconducting oxides or 2D materials
  • Back-end-of-line compatible memories (e.g. RRAM, PCM, MRAM, FeFET)
  • Computing-in-3D NAND or 3D NOR Flash
  • Silicon recrystallization methods for top tiers.
  • Monolithic 3D integration fabrication methods (e.g. layer transfer, sequential processing, nano-TSV)
  • Prototypes of monolithic 3D circuit primitives (e.g. 3D SRAM)
  • Design automation of monolithic 3D architectures (e.g. EDA flow for 3D physical layout)
  • Thermal modeling and simulations of monolithic 3D architectures
  • Heat spreading materials and embedded cooling for monolithic 3D architectures
  • System-level design and benchmarking for monolithic 3D architectures
  • System-Circuit-device co-design for energy-efficient monolithic 3D architectures

Important Dates

  • Open for Submission: February 15th, 2021
  • Submission Deadline: April 15th, 2021
  • First Notification: May 15th, 2021
  • Revision Submission: May 31th, 2021
  • Final Decision: June 15st, 2021
  • Publication Online: July 1st, 2021

Submission Guidelines

The IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC) IS AN OPEN ACCESS ONLY PUBLICATION: Charge for Authors: $1,350 USD per paper. Paper submissions must be done through the ScholarOne Manuscripts website:

Guidelines for papers and supplementary materials, as well as a paper template, are provided at this website.

Inquiries for the JxCDC Journal should be sent to:  JXCDC@IEEE.ORG

JxCDC is sponsored by;

Solid-State Circuits Society                               Magnetics Society

Circuits & Systems Society                               Nanotechnology Council

Computer Society                                             Electron Devices Society

Council on Electronic Design Automation

Council on Superconductivity


Papers can have 2 parts – the first part is a 4-8 page main paper (following a strict format – template available from website), and the second part is the supplementary material.  The main paper itself will just focus on describing why the work is important, the state of the prior art, the key new accomplishment(s) or results, and then what the research directions are going forward. The main paper can have an accompanying supplementary material (detailed methods) part.  The supplementary material is not mandatory, but authors are strongly encouraged to submit supplementary material, which will increase the chance of acceptance. The Supplementary material (detailed methods) will be peer reviewed along with the main paper.

Style guidelines for the main paper:

The main report (min. of 4, max. of 8) is written in format of a letter.  Due to their letter nature, the research must be original and must be of interest to research scientists/engineers and industry in related fields.

Abstract guidelines: The report begins with a fully referenced paragraph, ideally 200 words aimed at readers in the general area of engineering and physical sciences. The references must be up-to-date (e.g. referring to the best available materials, devices, circuits) & convey the relevance and originality of the research. This paragraph starts with a 3-4 sentence basic introduction to the problem area explaining the relevance and the issues.  This is followed by a one-sentence statement of the main conclusions (e.g. ‘Here we show’ or equivalent phrase); and finally, 2-3 sentences putting the main findings into general context so it is clear how the results described in the paper have moved the field forwards.

Body: The text of the article must be succinct and start with general audience and progressively increase the complexity for experts. The body of the main paper must provide clear context to the present work based on established industry roadmaps, figures of merit or generally accredited framework (computational throughputs, leakage power, long form Reviews of Modern physics, IEEE proceedings, Nobel lectures). To enable the comparison it is encouraged that key quantitative findings of the paper are compared in a table with current references.   Any concluding statements at the end of the article must be short since key conclusion is clearly articulated at the introduction. A repetition of the conclusions in the abstract should be avoided. Concluding statements explaining future possibilities or evolution are encouraged.

Style guidelines for supplementary material (methods paper):

The supplementary material is a unique format to encourage complete and clear communication of the relevant information to the experts in the area, while providing a citable source for the students for the innovations in scientific method: processing, modeling and theory. Long form derivations and code submissions are encouraged for theoretical and modeling papers. Modeling papers could for example provide all relevant data (not necessarily the code but they could) required to reproduce or validate the results. The JxCDC encourages the authors to put the experimental details such as fabrication methods, detailed characterizations, models or simulation methods (if it is a theory paper). The supplementary information therefore documents innovations in the experimental and modeling scientific methods, e.g. an innovative process technique to avoid interface effects, newly adopted differential equation solvers or innovative developments in device/circuit analysis can be included (and students/researchers will have a citable source online). Background materials that help the reader can be referenced in the supplemental material.

The supplementary material part begins with an unreferenced abstract (typically 150 words) and is divided into separate sections for introduction, results, discussion and methods. Introduction and discussion are brief and focused. The results section usually contains a general description followed by their validation. The methods section provides technical details necessary for the independent validation of the methodology, without referring to a chain of bibliographical references. The text of the supplementary material (excluding abstract, methods, references and figure legends) is limited to 6000 – 7000 words.  Articles have no more than 12 display items (figures and tables). The results and methods should be divided by topical subheadings; the discussion may contain subheadings at the author’s discretion.   If statistical testing was used to analyze the data, the methods section can contain a subsection on statistical analysis. If significant EDA tools are employed, relevant validation can be provided for the novel approach. The experimental tools and the instrumentation used must be explained in a clear schematic preferably with the models (part numbers) mentioned.

In summary, all the new contributions and accomplishments are to be summarized in the 4 to 8 page main paper. The main paper format will be such that it can be understood by not only the expert but also the non-expert (providing the context to someone unfamiliar but wanting to follow progress in the field). All experimental or simulation methods to enable reproducing/validating the results of the paper are in the supplementary material (detailed methods) part.