Edward S. Davidson received a BA in mathematics (Harvard University, l96l), an MS in communication science (University of Michigan, l962), and a PhD in electrical engineering (University of Illinois, l968). After working at Honeywell (’62-65), and on the faculties of Stanford University (’68-73) and the University of Illinois (’73-87), he joined The University of Michigan as professor of EECS in ’88, served as its chair through 1990, as associate chair for computer science and engineering (1997-2000), and was appointed professor emeritus in June 2000. He managed the hardware design of the Cedar parallel supercomputer at Illinois’ Center for Supercomputing Research and Development (1984-87) and directed Michigan’s Center for Parallel Computing (1994-97). He supervised 49 PhD and 38 MS students.
His research interests include computer architecture, parallel and pipeline processing, performance modeling, intelligent caches, supercomputing, and application code assessment and tuning. With his graduate students, he developed the reservation table approach to optimum design and cyclic scheduling of pipelines, designed and implemented an 8 microprocessor symmetric multiprocessor (SMP) system in 1976, and developed a variety of systematic methods for computer performance evaluation and enhancement, including early work on simulated annealing, wave pipelining, multiple instruction stream pipelines, decoupled access-execute architecture, and software pipelining. His most recent research focused on analyzing and improving the performance of application codes on parallel, vector, and workstation architectures, and on intelligent cache design and management, pipeline design, and prefetching.
He acquired industrial experience in computer architecture and design at Honeywell, Hewlett-Packard, and IBM. He has served as a technical consultant to industry and government agencies, including U.S. Army Electronics Command, Honeywell, Office of Naval Research, Sperry, Defense Nuclear Agency, General Electric, and Digital Equipment Corporation. He has served on advisory boards for universities, industry, and government agencies including Northwestern EE Department, Princeton EE Department, Nexgen Microsystems, Cydrome, Ardent, NCR, National Science Foundation, and University of Southern California.
He was elected Fellow of the IEEE (1984) for “contributions to the use of pipeline structures in computer architecture” and Chair of ACM-SIGARCH (l979-l983). He received the IEEE Computer Society’s Harry M. Goode Memorial Award (1992) for “pivotal seminal contributions to the design, implementation, and performance evaluation of high performance computer systems.”
In 2000 he received the highest professional society award in computer architecture, the Eckert-Mauchly Award given jointly by the IEEE Computer Society and the ACM, “for his seminal contributions to the design, implementation, and performance evaluation of high performance pipelines and multiprocessor systems.”
1996 Taylor L. Booth Award
“For contributions to the establishment of computer engineering as an academic discipline and for nurturing many leaders of this field during their formative years the profession.”
Learn more about the Taylor L. Booth Award
1992 Harry H. Goode Memorial Award Recipient
“For pivotal seminal contributions to the design, implementation, and performance evaluation of high performance computer systems.”
Learn more about the Harry H. Goode Memorial Award