CLOSED Call for Papers: Special Section on Defect and Fault Tolerance in Nanoscale Systems for Emerging Computing Paradigms and Applications

Authors are invited to submit a manuscript to the special section on Defect and Fault Tolerance in Nanoscale Systems for Emerging Computing Paradigms and Applications. Relevant topics of interest to this special section include (but are not limited to) reliability and dependability-aware analysis and design methodologies:

1. Yield Analysis and Modeling: Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics.
2. Testing Techniques: Built-in self-test; delay fault modeling and diagnosis; testing for digital, analog and mixed circuits; online testing; signal and clock integrity.
3. Error Detection, Correction, and Recovery: Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural and system-level techniques.
4. Dependability Analysis and Validation: Fault injection techniques and frameworks by simulation, emulation and particle and laser attack; dependability and characterization of error cross-section.
5. Repair, Restructuring and Reconfiguration: Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA systems.
6. Defect and Fault Tolerance: Reliable circuit/system synthesis; fault tolerant processes and design; design space exploration for dependable systems; permanent and transient faults.
7. Radiation effects: TID, DD and SEEs on nanotechnologies; modeling of radiation environments; radiation experiments; radiation hardening techniques.
8. Aging and Lifetime Reliability: Aging characterization and modeling; design and run-time reliability, thermal, and variability management and recovery.
9. Design for Security: Fault attacks, side-channel attacks, fault tolerance-based countermeasures, scan-based attacks and countermeasures, hardware trojans, security vs. reliability, interaction between VLSI test, trust, and reliability.

The reliability and dependability-aware design methodologies can extend to the entire computing continuum, including current and future nanoscale systems, computing architectures and applications:

1. For entire computing continuum: FPGAs, SoCs, NoCs, ASICs, low power microcontrollers, multicore processors, GPUs, embedded computing platforms, hardware accelerators, Internet of Things (IoTs), Cyber-Physical Systems (CPS), high-performance computing (HPC) platforms
2. For emerging technologies and architectures: 2.5D/3D ICs, quantum computing, memristors, spintronics, microfluidics, neuromorphic, stochastic/approximate architectures, Bayesian computing etc.
3. For different Applications and Case Studies: Life, safety and mission-critical applications (medical/healthcare, transportation, telecommunications, avionics and space, autonomous systems, industrial control, etc), Deep Neural Networks, AI in autonomous driving, AI in space, etc.

Schedule

- deadline for submissions: December 28, 2020 - first decision (accept/reject/revise, tentative): March 26, 2021 - submission of revised papers: May 28, 2021 - notification of final decision (tentative): July 30, 2021 - journal publication (tentative): first half of 2022

Submission Guidelines

Submitted papers must include new significant research-based technical contributions in the scope of the journal. Purely theoretical, technological, or lacking methodological-and-generality papers are not suitable to this special section. The submissions must include clear evaluations of the proposed solutions (based on simulation and/or implementations results) and comparisons to state-of-the-art solutions. Papers under review elsewhere are not acceptable for submission. Extended versions of published conference papers (to be included as part of the submission together with a summary of differences) are welcome, but they must have at least 40% of new impacting technical/scientific material in the submitted journal version and there should be less than 50% verbatim similarity level as reported by a tool (such as CrossRef). Guidelines concerning the submission process can be found here. While submitting through ScholarOne, please select the option "SI: Defect and Fault Tolerance in Nanoscale Systems for Emerging Computing Paradigms and Applications." As per TETC policies, only full-length papers (10-16 pages with technical material, double column - papers beyond 12 pages will be subject to MOPC, as per CS policies) can be submitted to special sections. The bibliography should not exceed 45 items and each author’s bio should not exceed 150 words.

Guest Editors

For additional information, please contact the guest editors by sending an email to tetc.si.dfp@gmail.com.

• Luigi Dilillo, LIRMM, France (IEEE member)
• Gianluca Furano, ESA, Netherlands (IEEE member)
• Mihalis Psarakis, University of Piraeus, Greece (IEEE member)

Luigi Dilillo received the Diploma in Electronic Engineering from the Politecnico di Torino (Italy) in 2001. He next obtained his PhD in microelectronics at University of Montpellier. After a two years period, as research fellow at the University of Southampton (UK) in the Electronics and Computer Science Department, he worked on electronic circuit reliability at CEA (French Commission for Atomic Energy). At this moment, he is CNRS researcher at LIRMM laboratory. The fields of interest of his researches are Memory Test and Reliability, Power Aware Test, Radiation Impact on Electronics, Radiation monitoring, Space and Radiation Hardened Systems Design, Electronics working in harsh environment. He has been involved in the technical committee of the major conferences of the test and radiation domain (IEEE European Test Symposium; IEEE RADGROUND in European Radiation Effects on Components and Systems Conference; EEE/ACM Design Automation and Test in Europe DATE; etc.). He has been the Program Chair of the IEEE DTIS2020, DFT20 events, general chair of DTIS 2021. M. Dilillo has participated to several European research projects (MEDEA+ ASSOCIATE, MEDEA+ NanoTEST, CATRENE TOETS). He has been technical responsible for HAMLET (ANR) project at LIRMM; initiator and scientific coordinator of MTCUBE project (funded by ESA). He is member of the scientific and organization board of CNRS GDR ERRATA (Effets des Radiations au Niveau Atmosphérique et Terrestre) and Chair of "Pole Electronique" at Centre Spatiale Universitaire de Montpellier. He is co-author of three books, 54 journal papers and 160 international conference and symposium papers, with three best paper awards. Gianluca Furano has worked in the European Space Agency’s Data System Division since March 2003. He is in charge of research and development activities and of supporting ESA projects and missions in the field of spacecraft data systems and the related architectures. Among Gianluca's interests are on-board computers and their major components, such as microprocessors and support components, meeting very stringent requirements in terms of radiation tolerance, reliability, availability, and safety; key avionics building blocks such as platform mass memories, remote terminal units, on-board buses and data networks; on-board and space to ground data communication protocols, including protocol security aspects. Gianluca also provides support to European standardization (CCSDS, ECSS) in areas such as telemetry, telecommand and on-board data, wireless and monitoring and control interfaces. Mihalis Psarakis received the diploma in computer engineering from the Department of Computer Engineering and Informatics, University of Patras, Greece and the PhD degree in computer science from the Department of Informatics and Telecommunications, University of Athens, Greece. Currently, he is an assistant professor in the Department of Informatics, University of Piraeus, Greece where he is leading the Embedded Systems Lab. His research interests include design, testing, and verification of embedded systems; microprocessors and systems-on-chip (SoCs); design of fault-tolerant embedded systems; fault tolerance methodologies for SRAM-based FPGAs; and design of FPGA-based accelerators. He has published more than 70 papers in peer reviewed transactions, journals, and conference proceedings. He has served as organizing and program committee member of numerous international conferences and symposiums (IEEE/ACM DATE, IEEE ETS, IEEE DFT, IEEE IOLTS, IEEE ISVLSI, NSREC, ARC). He has been the Program Chair of the IEEE DFT19 and DFT20 events. He is a member of the IEEE and the IEEE Computer Society.