Submission Due: 1 March 2027
Publication: September/October 2027
Cryptographic computing, including fully homomorphic encryption (FHE), secure multiparty computation (MPC), and zero-knowledge proofs (ZKPs), is increasingly becoming a practical and critical aspect of computing. Together, they enable computation over protected data, verifiable execution, privacy-preserving analytics, and even quantum-resistant security. These techniques have seen a surge of interest and advancement over the past decade thanks to research contributions spanning algorithms, software, and hardware. Yet, deployment remains costly: cryptographic workloads can still impose orders-of-magnitude overheads in computation, storage, communication, and energy.
These workloads differ from conventional applications. Many operate over large finite fields and polynomial rings; rely on number-theoretic transforms (NTTs), modular arithmetic, multiscalar multiplication, and hashing. These are each expensive to compute. Moreover, the level of complexity and slowdown of these workloads demands full system consideration, rather than piecewise optimization. Interactions between algorithms, compilers, runtimes, operating systems, memory and storage hierarchies, communication, and hardware must all be optimized together to alleviate the remaining performance overhead. Recent research has proposed hardware accelerators for FHE, ZKP proving, and MPC, have considered near-data-processing (NDP) and processing-in-memory (PIM), ISA extensions, and compiler optimizations, and high-performance GPU implementations.
This IEEE Micro Special Issue aims to bridge the cryptography and computer architecture communities and bring together academic researchers and industrial practitioners working across the full stack of cryptographic computing. We invite original contributions on systems that execute cryptographic computing, including system-level, architectural, microarchitectural, compiler, runtime, and algorithm–system co-design. We encourage work that connects protocol design to real implementation constraints, develops shared methodologies and benchmarks, reports rigorous quantitative evaluation, and demonstrates how new systems make previously impractical applications deployable. Visionary perspectives, production experiences, and carefully supported negative results are also welcome when they yield broadly useful insights.
Topics of interest include, but are not limited to:
Scope note. Submissions should make a clear systems, architecture, or implementation contribution and quantitatively evaluate its impact. Purely cryptographic constructions without substantial computing-systems insight are outside the intended scope; new cryptographic methods are welcome when they are developed or evaluated in close connection with implementation, deployment, or full-stack design.
For author information and guidelines on submission criteria, please visit the Author Information Page. Please submit papers through the IEEE Author Portal, and select, "Systems for Cryptographic Computing." Manuscripts should not be published or currently submitted for publication elsewhere. Please submit only full papers intended for review, not abstracts, to the IEEE Author Portal.
Manuscripts must not exceed 6,000 words, including references, biographies, tables, and figures with captions; each average-size figure counts as 250 words. Abstracts should be no more than 150 words. Manuscripts must not have been previously published or be under review elsewhere, and extensions of conference papers must contain at least 30 percent new material. Authors should clearly identify the new contribution relative to any preliminary version.