CLOSED: Call for Papers: Special Issue on Cache Coherent Interconnects and Resource Disaggregation Techniques

Publication: May/Jun 2025

In the era of exponential data growth, modern data centers and large-scale computing environments are challenged by the limitations of traditional, monolithic system designs that tightly integrate compute, memory, and storage resources. These conventional, all-integrated systems confront significant difficulties including resource over-provisioning, under-utilization, and hitting the memory capacity wall, highlighting the urgent need for innovative architectures. Resource disaggregation emerges as a compelling paradigm, promising to break down such monolithic system architectures into pools of shared, distributed resources. However, the transition to disaggregated resources introduces its own set of challenges, including the need for significant code refactoring, potential performance penalties, substantial new hardware investments, increased complexity in system maintenance, and security concerns. Amidst this landscape, cache coherent interconnects, like Intel’s Ultra Path Interconnect (UPI)/QuickPath Interconnect (QPI), AMD's Infinity Fabric, and Compute Express Link (CXL), offer a promising solution for disaggregated resources. By facilitating efficient access to remote memory through cache coherence for minimal latency and overhead, these interconnects are poised to significantly enhance the feasibility of resource disaggregation. This special issue of IEEE Micro seeks articles on the cutting-edge developments in cache coherent interconnects and their role in enabling resource disaggregation across computing, memory, and storage. Topics include, but are not limited to:

• Coherent Interconnect Protocols and Models for Resource Disaggregation Systems.
• Software/Hardware Co-Designs for High-Performance Disaggregated Coherency Management.
• Processor/Accelerator Designs Oriented towards Management in Coherent Disaggregated Systems. 
• Application-Architecture Co-Designs, Exploiting Coherent Disaggregation Techniques.
• Reliability, Testability, and Debuggability of Coherent Disaggregation Systems.
• Applications Based on Coherent Interconnects and Disaggregated Systems.

Important Submission Instructions:

As of 20 November 2024, IEEE Micro will use the IEEE Author Portal for all new submissions.

• If you have not yet started the submission process, please use the IEEE Author Portal to submit your article.
• If you have started a draft of your submission OR if you submitted your paper prior to the IEEE Author Portal launch, you will finish the peer review life cycle of submission(s) currently under review through ScholarOne Manuscripts. You do not need to submit a new manuscript. All new and future submissions will be submitted entirely through the IEEE Author Portal.

Please be sure to select the special issue or special section name when you submit your article. Manuscripts should not be published or currently submitted for publication elsewhere. Please submit only full papers intended for review, not abstracts. For author information and guidelines on submission criteria, please visit IEEE Micro‘s Author Information page.

Questions?

Contact the Guest Co-Editors or the editor-in-chief Hsien-Hsin Sean Lee

• Wonil Choi, Hanyang University, Ansan, Korea
• Jie Zhang, Peking University, Beijing, China