Transactions on Computers Media Center

Our volunteers share with the wider community their views and experiences on a variety of topics. The volunteers can range from associate editors to authors, reviewers or members from the research community at large. The interviews are intended to cover a wide spectrum of topics that are relevant to our community. These topics can be in the form of "shared experiences" and "lessons learned" or highlighting a new technological or theoretical breakthrough. We hope that members of the community will actively participate in making this new feature a great success. For information on submitting multimedia content, please click here.

Albert Zomaya

TC EIC

 

A Word from the Editor-in-Chief,
Albert Y. Zomaya

 

 

 

Call for Papers: IEEE Transactions on Computers Special Section on Computer Arithmetic

Guest Editors Alberto Nannarelli, Peter-Michael Seidel, and Ping Tak Peter Tang [http://www.computer.org/portal/web/tc] seeking original manuscripts for the IEEE Transactions on Computers Special Section on Computer Arithmetic. Submission deadline: September 15, 2013.

 

Computer arithmetic is fundamental to the design of general-purpose and domain-specific processors. Novel arithmetic algorithms and hardware designs are needed to satisfy the power-performance requirements of numerically-intensive applications in a variety of areas including scientific computing, cryptography, multimedia, graphics and digital signal processing. Specialized number representations and encodings play a significant role in the design of arithmetic algorithms and their implementations. Additionally, understanding the fundamental properties of finite precision number systems is essential in the engineering of efficient arithmetic algorithms, as well as the current and future emerging technologies are important in influencing the design and the implementation of such algorithms.

The full Call for Papers can be found here: http://www.computer.org/cms/Computer.org/transactions/cfps/cfp_tcsi_arith.pdf

In Their Own Words In Their Own Words
A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing

by Luca Sterpone, Mario Porrmann, Jens Hagemeyer

 

Reconfigurable hardware is gaining a steadily growing interest in the domain of space applications. The ability to reconfigure the information processing infrastructure at runtime together with the high computational power of today's FPGA architectures at relatively low power makes these devices interesting candidates for data processing in space applications. Partial dynamic reconfiguration of FPGAs enables maximum flexibility and can be utilized for performance optimization, for improving energy efficiency, and for enhanced fault tolerance. To be able to prove the effectiveness of these novel approaches for satellite payload processing, a highly scalable prototyping environment has been developed, combining dynamically reconfigurable FPGAs with the required interfaces such as SpaceWire, MIL-STD-1553B, and SpaceFibre. The developed systems have been enabled to space harsh environments thanks to an analytical analysis of the radiation effects on its most critical reconfigurable components. Aiming at that scope, a new algorithm for the analysis of critical radiation effects, in particular, related to Single Event Upsets (SEUs) and Multiple Event Upsets (MEUs) has been developed to obtain an effective estimation of the radiation impact and enabling the tuning of the component mapping reducing the routing interaction between the reconfigurable placed modules in their different feasible positions. The experimental performance of the system has been evaluated by a proper dynamic reconfiguration scenario, demonstrating a partial reconfiguration at 400 MByte/s, blind and readback scrubbing is supported and the scrub rate can be adapted individually for different parts of the design. The fault tolerance capability has been proven by means of a new analysis algorithm and by fault injection campaigns of SEUs and MCUs into the FPGA configuration memory.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2013.80

The Cost of Privatization in Software Transactional Memory

by Hagit Attiya, Eshcar Hillel

 

Software transactional memory (STM) is a promising approach for programming concurrent applications; STM guarantees that a transaction, consisting of a sequence of operations on the memory, appears to execute atomically. In practice, however, it is important to be able to run transactions together with nontransactional legacy code accessing the same memory locations, by supporting privatization of shared data. Privatization should be provided without sacrificing the parallelism offered by today’s multicore systems and multiprocessors. This paper proves an inherent cost for supporting privatization, which is linear in the number of privatized items. Specifically, we show that a transaction privatizing k items must have a data set of size at least k, in an STM with invisible reads, which is oblivious to different non-conflicting executions and guarantees progress in such executions. When reads are visible, it is shown that r memory locations must be accessed by a privatizing transaction, where r is the minimum between k, the number of privatized items, and the number of concurrent transactions guaranteed to make progress. This captures, in a concrete and quantitative manner, the tradeoff between the cost of privatization and the level of parallelism offered by the STM.

The full article can be found here: http://doi.ieeec omputersociety.org/10.1109/TC.2012.159

Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip

by H. Kim, B. Grot, P. V. Gratz, D. Jimenez

 

As processor chips become increasingly parallel, an efficient communication substrate is critical for meeting performance and energy targets. In this work, we target the root cause of network energy consumption through techniques that reduce link and router-level switching activity. We specifically focus on memory subsystem traffic, as it comprises the bulk of NoC load in a CMP. By transmitting only the flits that contain words predicted useful using a novel spatial locality predictor, our scheme seeks to reduce network activity. We aim to further lower NoC energy through microarchitectural mechanisms that inhibit datapath switching activity for unused words in individual flits. Using simulation-based performance studies and detailed energy models based on synthesized router designs and different link wire types, we show that (a) the prediction mechanism achieves very high accuracy, with an average rate of false-unused prediction of just 2.5%; (b) the combined NoC energy savings enabled by the predictor and microarchitectural support are 36\% on average and up to 57% in the best case; and (c) there is no system performance penalty as a result of this technique.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2012.238

Constructing Connected-Dominating-Set with Maximum Lifetime in Cognitive Radio Networks

by Zhiyong Lin, Hai Liu, Xiaowen Chu, Yiu-Wing Leung, Ivan Stojmenovic

 

Connected-dominating-set (CDS) is a representative technique for constructing virtual backbones of wireless networks and thus facilitates implementation of many tasks including broadcasting, routing, etc. Most of existing works on CDS aim at constructing the minimum CDS (MCDS), so as to reduce the communication overhead over the CDS. However, MCDS may not work well in cognitive radio networks (CRNs) where communication links are prone to failure due to stochastic activities of primary users (PUs). A MCDS without consideration of the stochastic activities of PUs easily becomes invalid when the PUs become active. This study addresses a new CDS construction problem by considering the PUs’ activities. Our problem is to maximize the lifetime of the CDS while minimizing the size of the CDS, where the lifetime of a CDS is defined as the expected duration that the CDS is maintained valid. We show that the problem is NP-hard and propose a three-phase centralized algorithm. Given a CRN, the centralized algorithm can compute a CDS such that the lifetime of the CDS is maximized (optimal), and the size of the CDS is upper-bounded. We further present a two-phase localized algorithm which requires 2-hop information. Extensive simulations are conducted to evaluate the proposed algorithms.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2013.77

Dynamic Backlight Scaling Optimization: A Cloud-Based Energy-Saving Service for Mobile Streaming Applications

by Chun-Han Lin, Pi-Cheng Hsiu, and Cheng-Kang Hsieh

 

This video introduces a cloud-based energy-saving service, called the dynamic backlight scaling service, which minimizes the backlight’s energy consumption when displaying video streams on mobile devices without adversely impacting the user’s visual experience. This video also provides a demonstration designed to validate the practicability of the proposed approach.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2012.210

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Essential Sets: Industry's Interest in Computer Arithmetic Research: Part I, Dr. Schwarz's view

Dr. Eric Schwarz describes the important aspects of computer arithmetic research. He provides a list of current questions that need to be solved by research and also what topics are the most interesting to industry.

 

Purchase the Essential Sets here:

Volume 1:

www.computer.org/portal/web/store?product_id=ES0000033&category_id=TechSets

Volume 2:

www.computer.org/portal/web/store?product_id=ES0000034&category_id=TechSets

 

Essential Sets: Industry's Interest in Computer Arithmetic Research: Part II, Dr. Hu's view

Dr. Hu describes the important aspects of computer arithmetic research. He provides a list of current questions that need to be solved by research and also what topics are the most interesting to industry.

Purchase the Essential Sets here:

Volume 1:

www.computer.org/portal/web/store?product_id=ES0000033&category_id=TechSets

Volume 2:

www.computer.org/portal/web/store?product_id=ES0000034&category_id=TechSets

 

Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems

Guest editor Cecilia Metra discusses the "Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems" theme issue for IEEE Transactions on Computers. View the issue here:

http://www.computer.org/portal/web/csdl/transactions/tc#3