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ABSTRACT
Manufacturing defects in nanoscale tech- nologies have highly complex timing behaviour that is also aected by process variations. While conventional wisdom suggests that it is optimal to detect a delay defect through the longest sensitisable path, non-trivial defect behaviour along with modelling inaccuracies necessitate consideration of paths of well-controlled length during test generation. We present a generic methodology that yields tests through all sensitisable paths of user-specied length. The resulting tests can be employed e.g. within the framework of adaptive testing. The methodology is based on encoding the problem as an instance of the Boolean Satisability Problem (SAT) and thereby leverages recent advances in SAT-solving technology.
CITATION
S. Hillebrecht, "SAT-based Analysis of Sensitisable Paths", IEEE Design & Test of Computers, , no. 1, pp. 1, PrePrints PrePrints, doi:10.1109/MDT.2012.2230297
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