Prof. Jiang Xu

Hong Kong University of Science and Technology
Department of ECE HKUST
Clear Water Bay, Kowloon
Hong Kong
Phone: +853 2358-5036
Fax: +852 2358-1485

DVP term expires December 2013

Jiang Xu received his MA and PhD degrees in Electrical Engineering from Princeton University, and received BS and MS degrees in Electrical Engineering from Harbin Institute of Technology. His research areas include multiprocessor system-on-chip, computer architecture, low-power VLSI design, and HW/SW codesign. From 2001 to 2002, he worked at Bell Labs USA as a Research Associate and discovered the First Generation Dilemma in platform-based SoC design methodologies. Prof. Xu was a Research Associate at NEC Laboratories America from 2003 to 2005 and working on networks-on-chip architectures and implementations. He joined a startup
company, Sandbridge Technologies, in 2005 and developed two generations of ultra-low power multiprocessors for mobile platforms. Since 2007, Prof. Xu joined the Department of Electronic and Computer Engineering in Hong Kong University of Science and Technology as an Assistant Professor, and established the Mobile Computing System Lab. He has published more than 30 papers in peer-reviewed journals and conferences, and received one Best Paper Award. Prof. Xu serves on the organizing and technical committees in many international conferences, including ICCD, CASES, ISVLSI, VLSI, EMSOFT, VLSI-SoC, ICESS, RTCSA, NOCS, ESO, etc. He currently serves as an Associate Editor of ACM Transactions on Embedded Computing Systems.

More info about Prof. Xu can be found at

Optical Network-on-Chip for Next Generation On-Chip Multiprocessor Systems
As the number of transistors available on a single chip increases to billions or even larger numbers, on-chip multiprocessor systems are becoming attractive choices for high-performance and low-power applications. Traditional on-chip communication architectures for multiprocessor systems face several issues, such as poor scalability, limited bandwidth, and high power consumption. Networks–on-chip (NoCs) relieve multiprocessor systems from these issues by using modern communication and networking theories. Many NoCs have been studied, and most of them are based on metallic interconnects and electronic routers. As new applications continuously push the limits of multiprocessor systems, the conventional metallic interconnects and electronic routers gradually become the bottlenecks of NoC performance due to the limited bandwidth, long delay, large area, high power consumption, and crosstalk noise.

Optical interconnects have demonstrated their strengths in multicomputer systems, on-board inter-chip interconnect, and the switching fabrics of Internet routers. Silicon-based optical waveguides can be used to build on-chip optical interconnects. The progress in photonic technologies, especially the development of microresonators, makes optical on-chip routers possible. This talk will present our recent studies on optical NoCs. Optical NoCs use silicon-based optical interconnects and routers, which are compatible with CMOS technologies. Our studies show that they are promising candidates to achieve significant higher bandwidth, lower power, lower interference, and lower delay compared with electronic NoCs.

On-Chip Sensor Network: A Systematic Approach to Detect, Report, and Alleviate Run-Time Threats in Multiprocessor System-on-Chip
Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on multiprocessor system-on-chip (MPSoC) to satisfy the increasing demands of applications. However, it also makes MPSoC more susceptible to various reliability threats, such as high temperature and power/ground (P/G) noise. As the scale and complexity of MPSoC continuously increase, a systematic approach that not only detects reliability threats but also mitigates such threats accordingly at run time could potentially offer better performance, scalability, and flexibility for MPSoC designs.

This talk will present a systematic approach, on-chip sensor network (SENoC), to collaboratively detect, report, and alleviate run-time threats in MPSoC. SENoC not only detects reliability threats and shares related information among PUs, but also plans and coordinates the reactions of related PUs in MPSoC. To highlight the details of our idea, SENoC is used and explained in a case study on simultaneous switching noise in MPSoC’s P/G network during power gating. Based on the detailed noise behaviors under different scenarios derived by a circuit-level MPSoC P/G noise simulation and analysis platform, simulation results show that SENoC can offer an effective solution to this issue.