Prof. Mohammad Tehranipoor

Department of Electrical and Computer Engineering
University of Connecticut
371 Fairfield Way, Unit 2157
Storrs, CT 06269-2157
Phone: 860-486-3471
Fax: 860-486-2447

DVP term expires December 2013

Mohammad Tehranipoor is currently an Associate Professor of Electrical and Computer Engineering at the University of Connecticut. His current research projects include: computer-aided design and test for CMOS VLSI designs, Reliable systems designat nanoscale, design-for-testability, at-speed test, secure design and IC trust. Dr. Tehranipoor has published over 105 journal articles and refereed conference papers in the above. He has published two books entitled “Nanometer Technology Designs – High-Quality Delay Tests” and “Emerging Nanotechnologies – Test, Defect Tolerance and Reliability” in addition to seven book chapters. He is a recipient of a best paper award at the 2005 VLSI Test Symposium (VTS), best paper award at the 2008 North Atlantic Test Workshop (NATW), best paper award at NATW’2009,  honorable mention for best paper award at NATW’2008, best paper candidate at the 2006 Design Automation Conference (DAC), best paper candidate at the 2005 Texas Instrument Symposium on Test, best panel award at VTS’2006, and top ten paper recognition at the 2005 International Test Conference (ITC). Dr. Tehranipoor is also a recipient of the 2008 IEEE Computer Society (CS) Meritorious Service Award, the 2010 IEEE CS Most Successful Technical Event for co-founding and chairing HOST Symposium, the 2009 NSF CAREER award, and the 2009 UConn ECE Research Excellence Award.

He serves on the program committee of several leading conferences and workshops. Dr. Tehranipoor served as the guest editor for Journal of Electronic Testing: Theory and Applications (JETTA) and IEEE Design and Test of Computers. He served as Program Chair of the 2007 IEEE Defect-Based Testing (DBT) workshop, Program Chair of the 2008 IEEE Defect and Data Driven Testing (D3T), Co-program Chair of the 2008 International Defect and Fault Tolerance Symposium in VLSI Systems (DFTS), and General Chair for D3T-2009 and DFTS-2009. He co-founded a new workshop called IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) and served as HOST-2008 and HOST-2009 General Chair and Chair of Steering Committee. He is currently serving as Vice-general Chair for the 2011 IEEE North Atlantic Test Workshop (NATW), an Associate Editor for JETTA, an Associate Editor for IEEE Design and Test of Computers, an Associate Editor for Journal of Low Power Electronics (JOLPE), an Editor for TTTC Newsletter, and an ACM Distinguished Speaker. He is a term member of Graduate Faculty of ECE Department at Duke University. Dr. Tehranipoor is a Senior Member of the IEEE and Member of ACM and ACM SIGDA.

Toward Design of Trusted Hardware
Design and fabrication of integrated circuits (ICs) are becoming increasingly vulnerable to malicious activities and alterations with globalization. These vulnerabilities have raised serious concerns regarding possible threats to military systems, financial infrastructures, transportation security, household appliances, etc. An adversary can introduce a Trojan designed to disable and/or destroy a system at some future time (time bomb) or the Trojan may serve to leak confidential information covertly to the adversary. Trojans can be implemented as hardware modifications to application-specific ICs (ASICs), commercial-off-the-shelf (COTS) parts, microprocessors, or digital-signal-processors (DSPs), or as firmware modifications, e.g., to field programmable gate arrays (FPGA) bitstreams. Trojans are cleverly hidden by the adversary to make it extremely difficult for chip validation processes, such as manufacturing test, to accidentally discover them using random/structural/functional patterns.

In this talk, we will present various vulnerabilities to the IC/IP design and fabrication processes. Effective techniques will be presented for detecting and locating malicious alterations, e.g. the insertion of Trojans, during IP core design, wafer probe and/or package test as a means of improving the level of trustworthiness of the chips. A comprehensive trusted design methodology is presented to increase the probability of detection of hardware Trojans. The proposed methods are based on analyzing side-channel signals in integrated circuits namely path delay and power supply transient current as well as detecting them via full activation.

Reliable Systems Design at Nanoscale
Abstract: Technology scaling to 45nm and below has made reliability and variability the dominant design and test challenges to the semiconductor and EDA industry. Aging and wearout-related errors (negative and positive bias temperature instability (BTI), oxide breakdown, channel hot-carrier injection (HCI) and electromigration) usually manifest as temporal degradation of circuit performance during its lifetime. In addition, technology scaling has led to very large variations in transistors and interconnects geometry that are difficult to model and can result in unpredictable range of variations in circuit specification. Furthermore, aggressive scaling of transistor dimensions can lead to statistical variation of aging-induced degradation. The solution to the above problems, in practice, has traditionally been to perform aggressive guardbanding and improve process technology to bypass the analysis and optimization of these effects.

In this talk, we will first briefly describe fundamental reliability problems at nanometer technology designs. Next, we will present our NBTI, delay, process and IR sensors added to a 55nm technology SOC chip. These sensors provide key reliability and variability information to designer to take proper measure for guardbanding as well as developing effective self-test and self-tuning methodologies for improving in-field reliability. We will then present methodologies for identifying critical reliability and variability paths for better performance guardbanding and on-chip self-calibration.

Test and Diagnosis for Timing- and Power-Related Failures for Nanometer Technology Designs
Prior to 100nm technology designs and the adoption of phase-shift masks, the largest dominating portion of the diagnosis pie chart was logic and the defect mechanism was particulate. However, at sub-100nm, the pie chart has changed significantly and the timing and power portions of the chart have become the dominant defect mechanisms. The changes in defect mechanisms and increased parametric sensitivity have changed the fault/defect detection strategies. As technology scales and functional frequency and density continue to rise, many factors and parameters have shown significant impact on design and test of chips. CAD and DFT engineers must deal with many new challenges introduced in nanotechnology such as IR-drop and power supply noise (PSN) effects on chip performance, signal integrity and crosstalk effects on path delay, excessive process variations, high test pattern volume, low fault/defect coverage, and effective small delay defect test pattern generation and fault simulation.

In this talk, we will first briefly address the new test challenges for nanometer technology designs, e.g. at-speed test, small delay defects, crosstalk, power and IR-drop issues. We will then preset methods to take into account timing, power, crosstalk, and layout during pattern generation both for pre-tapeout design validation and post-manufacturing at-speed test and diagnosis.

Efficient Pattern Grading and Selection for Screening Small Delay Defects Considering Process Variations, Power Supply Noise and Crosstalk
Testing for small-delay defects (SDDs) is necessary to ensure the high quality products in smaller technology nodes. Current tools such as timing-unaware transition-delay fault (TDF) ATPGs and timing-aware ATPGs are not either efficient in detecting SDDs or suffer from large pattern count and CPU runtime. Furthermore, none of these methodologies take into account the impact of process variations and pattern-induced noises, e.g., power supply noise (PSN) and crosstalk, which are potential sources of SDDs. In this talk, we present new methodologies considering the impacts of pattern-induced noises to grade and select the most effective patterns for detecting SDDs. The grading procedure is performed on a large repository of patterns generated by N-detect TDF ATPG. Top-off ATPG is performed after pattern selection to ensure the same fault coverage as that for timing-aware ATPG.