About IEEE Transactions on Multi-Scale Computing Systems

Contact Information

Editor-in-Chief
Partha Pratim Pande
Professor
Boeing Centennial Chair in Computer Engineering
School of EECS, WSU
PO BOX 642752
Pullman, Washington 99164-2752
Phone: 509-335-5223
Fax: 509-335-3818
pande@eecs.wsu.edu
http://www.eecs.wsu.edu/~pande

TMSCS Publication Coordinator
IEEE Computer Society
10662 Los Vaqueros Circle
Los Alamitos, CA 90720, USA
EMAIL: TMSCS@computer.org
PHONE: +1.714.821.8380
FAX: +1.714.821.9975

Scope of TMSCS

The IEEE Transactions on Multi-Scale Computing Systems (TMSCS) is a peer-reviewed publication devoted to computing systems that exploit multi-scale and multi-functionality. These systems consist of computational modules that utilize diverse implementation scales (from micro down to the nano scale) and heterogeneous hardware and software functionalities; moreover, these modules can be based on operating principles and models that are valid within but not necessarily across their respective scales and computational domains. Contributions to TMSCS must address computation of information and data at higher system-levels for processing by digital and emerging domains. These computing systems can also rely on diverse frameworks based on paradigms at molecular, quantum and other physical, chemical and biological levels. Innovative techniques such as inexact computing, management/optimization of smart infrastructures and neuromorphic modules are also considered within scope.

This publication covers pure research and applications within novel topics related to high performance computing, computational sustainability, storage organization and efficient algorithmic information distribution/processing; articles dealing with hardware/software implementations (functional units, architectures and algorithms), multi-scale modeling and simulation, mathematical models and designs across multiple scaling domains and functions are encouraged. Novel solutions based on digital and non-traditional emerging paradigms are sought for improving performance and efficiency in computation. Contributions on related topics would also be considered for publication.


Editorial Board

Editor-in-Chief

Partha Pratim Pande - Washington State University

Associate Editors

Swarup Bhunia - Case Western Reserve University

Krishnendu Chakrabarty - Duke University

Chi On Chui - University California, LA

Petru Eles - Linköping University

Sathish Gopalakrishnan - University of British Columbia

Jörg Henkel - Karlsruhe Institute of Technology

Ravi Iyer - Intel

Niraj Jha - Princeton University

Jacques-Olivier Klein - Univ. Paris-Sud, France

Hai Li - University of Pittsburgh

Radu Marculescu - Carnegie Mellon University

Tadao Nakamura - Keio University

Ian O’Connor - Ecole Centrale de Lyon, Ecully, France

Sudeep Pasricha - Colorado State University

Anand Raghunathan - Purdue University

Sandip Ray - Intel

Sarma Vrudhula - Arizona State University


Steering Committee

Chair

Csaba Andras Moritz

IEEE Computer Society

Sorin Cotofana

Lei Wang

Michael Niemier

IEEE Communications Society

Stephen Bush

IEEE Nanotechnology Council

Dan Hammerstrom

Ramesh Karri