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Issue No.05 - September-October (2007 vol.24)
pp: 442-452
Mario R. Casu , Politecnico di Torino
ABSTRACT
Latency-insensitive design copes with excessive delays typical of global wires in current and future IC technologies. The goal is achieved through the encapsulation of synchronous logic blocks in wrappers that communicate via a latency-insensitive protocol (LIP) and pipelined interconnects. Previously proposed solutions suffer from excessive performance penalty in terms of throughput, or lack of generality. The authors present an adaptive version of an LIP that outperforms previous "static" implementations, as demonstrated through two relevant study cases: a microprocessor and an MPEG encoder, whose components are made insensitive to the latencies of their interconnections through a newly developed wrapper. This article also features an informal exposition of the theoretical basis of adaptive LIPs as well as implementation details.
INDEX TERMS
latency-insensitive protocols, wire pipelining, ICs, interconnections
CITATION
Mario R. Casu, "Adaptive Latency-Insensitive Protocols", IEEE Design & Test of Computers, vol.24, no. 5, pp. 442-452, September-October 2007, doi:10.1109/MDT.2007.152
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