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Issue No.04 - July/August (2007 vol.24)
pp: 362-372
Donghwi Lee , Stanford University
Intaik Park , Stanford University
Jeff Rearick , Advanced Micro Devices
ABSTRACT
The act of applying a scan-based delay test to a chip can cause electrical disturbances in the power and clock distribution networks that affect the results of the test, either for better or for worse. Empirical data presented in this study suggest that altering the details of the delay test application protocol can have a significant effect on the test results, and thus the yield of the product being tested. Specifically, inserting wait states between scan shifting and the launch clock results in measurable yield improvement. Although the exact mechanisms involved remain elusive, the authors were able to eliminate several possibilities through a series of experiments. It is clear from these experiments that yield recovery is a real phenomenon, and that launch delay (LD) tests can help to recover from IR drop.
INDEX TERMS
delay testing, ATPG, yield loss, false failure, structural test, functional test, IR drop
CITATION
Donghwi Lee, Erik Volkerink, Intaik Park, Jeff Rearick, "Empirical Validation of Yield Recovery Using Idle-Cycle Insertion", IEEE Design & Test of Computers, vol.24, no. 4, pp. 362-372, July/August 2007, doi:10.1109/MDT.2007.131
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