Intel Chips Step up to 3D
Intel has introduced 22-nm Tri-Gate chips that use a new process technology for patterning transistors in 3D. "We achieved twice the usual generational gain with the move to 3D," said Mike Mayberry, director of components research with Intel's Technology & Manufacturing Group.
The new design can improve performance by 37 percent owing to transitions from 32 to 22 nm technology and from a planar transistor to a 3D transistor. The new transistors will use less than half the power at the same performance as 2D 32 nm chips.
Intel plans to release the Ivy Bridge line of chips based on the new process later this year for servers, desktops, and laptops. Products for smart phones and other mobile devices will come later.
The main contributor to this improvement is the fully depleted operation of the transistor allowed by the transition to 3D, Mayberry said. The new transistor design raises electrical components up, thereby increasing the contact ratio between the control wires and active transistor material. This increased contact ratio provides a larger area for the electrons to move through and decreases the distances they must travel to leave the transistor. These features help fully deplete the electrons from the transistor when it's turned off, leading to more power efficiency and greater switching speed.
Intel's new design incorporates two fundamental advances in semiconductor fabrication methodologies: a 3D transistor design and a Tri-Gate controller.
The holy grail of 3D design is to stack multiple transistor elements on top of each other. One fundamental limitation of silicon chips is that most of the computing activity occurs across a 2D pattern within a very thin layer of electrical activity across the surface. By stacking multiple layers on top of one another, it becomes possible to multiply the chip's computing power by the number of layers and reduce the distance between compute elements.
But true stacked 3D chips face manufacturing challenges. The processes of etching the transistors and wires on a chip use extreme temperatures and caustic chemicals, which make it difficult to add many layers. However, the new Tri-Gate transistor features didn't require any major changes to the equipment set, just the addition of a few extra steps.
"This technology does not directly affect stacking at either wafer or die level," Mayberry explained. "For other 3D approaches, all of the chip steps are completed separately for the two wafers to be stacked. Stacking does not produce cost savings in the way that density improvements do."
Instead, Intel has slightly tuned its existing fabrication process to form taller transistor elements. This allows transistor control wires to be affixed to side surfaces, in addition to the top. This technique not only increases the surface area but also reduces the absolute distance between the control elements and the transistor's center. All these physical attributes combine to reduce the depletion rate by 10 times, which in turn reduces the power required to control the transistor and the time required to switch its state.
"A planar transistor carries most of the currents in the surface when it is turned on," Mayberry explained. "Since we've folded the channel surface, there is a density advantage as we pack more current into a smaller space. Further, since the 3D gate has better control of the whole of the channel, the transistor has better shut-off characteristics and that especially improves the performance at low voltage, which is a major power benefit.”
Both packing density and power performance gain from this structure. For instance, the SRAM cell size has been reduced by about 50 percent from 32 nm.
In theory, the three gates in the new chips could be wired separately and used to create new kinds of logical building blocks for chip designs. But at the moment, Intel plans to use only a single wire to drive all three gates to improve chip performance and power usage.
"We've investigated controlling each of the sides separately within the research projects but have not put those forward into development," Mayberry said. "In the version announced, the three gates share common wiring, and so there are no additional wires required. It's simply a case of there not being enough room for three wires."
But Richard Doherty, a chip design analyst with the Envisioneering Group, said that Intel might just be holding some advanced designs close to the vest. "They don't want to trigger any rival design awareness or alternative approaches that might challenge their early experience with three-wire controls," he said.
Just Another Step
"I'’s a notable iterative step, particularly in reducing switching-energy levels and wasted heat, but it's not quite the unique game changer Intel portrayed," said Doherty. He expects many other chip-manufacturers including IBM, Samsung. AMD, and others to use Intel's lessons to improve their own designs. "Intel will be facing a lot of process competition, which will be good for everybody. Intel has legitimized 3D structures, so others will have their own take on processes and technologies which benefit all future chip design options."
George Lawton is a freelance technology writer based in Guerneville, CA. Contact him at firstname.lastname@example.org.