From the July-December 2013 issue
High Performance, Energy Efficient Chipkill Correct Memory with Multidimensional Parity
By Xun Jian, John Sartori, Henry Duwe, Rakesh Kumar
It is well-known that a significant fraction of server power is consumed in memory; this is especially the case for servers with chipkill correct memories. We propose a new chipkill correct memory organization that decouples correction of errors due to local faults that affect a single symbol in a word from correction of errors due to device-level faults that affect an entire column, sub-bank, or device. By using a combination of two codes that separately target these two fault modes, the proposed chipkill correct organization reduces code overhead by half as compared to conventional chipkill correct memories for the same rank size. Alternatively, this allows the rank size to be reduced by half while maintaining roughly the same total code overhead.
Editorials and Announcements
- Editorial—Introducing the New Editor-in-Chief of the IEEE Computer Architecture Letters
- Editorial—A Message from the New Editor-in-Chief and Introduction of New Associate Editors
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