Edward B. Eichelberger

1989 W. Wallace McDowell Award Recipient

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"For developing the level-sensitive scan technique of testing solid-state logic circuits and for leading, defining, and promoting design for testability concepts"

 

Dr. Eichelberger is an IBM Fellow and Manager of Advances VLSI Technology and Testing at the IBM Mid-Hudson Valley Laboratories in Kingston.  He has worked and published in the areas of VLSI chip design, circuit design, design automation and design for testability.

Edward B. Eichelberger received his B.S. in electrical engineering from Lehigh University in 1956.  He joined IBM after graduation to work in solid state circuit design at the Endicott Product Development Laboratory.  In 1959, he began graduate study at Princeton University under the IBM Resident Graduate Study Program.  While at Princeton, he worked in the field of switching theory and received his M.A. and Ph.D. degrees in electrical engineering in 1963.  Dr. Eichelberger then resumed his duties at the laboratory in Endicott.  At the time he published his paper on hazard detection in combinational and sequential circuits in 1965, he was serving as the manager of scientific computation, where he no doubt observed the large amounts of computer time consumed for simulation and test generation.

Taking a more active role in influencing the design of circuits, he developed the concepts of level-sensitive scan design.  It was then necessary to convince designers and their mangers that LSI required new techniques for testing and these must be designed from the beginning.  Teaming up with Tom Williams the concepts were ultimately accepted.

Since 1977, he has managed various custom design VLSI projects in both FET and bipolar technologies.  Dr. Eichelberger has published extensively and holds 16 U.S. patents, four of which are joint with Dr. Williams.

Among his honors, Dr. Eichelberger was elected an IEEE Fellow in 1986.  He received an IBM Outstanding Contribution Award for the "Level sensitive Scan Design" (LSSD) technique in 1973, and also an Outstanding Innovation Award for Weighted Random Patterns.

 

Thomas W. Williams

1989 W. Wallace McDowell Award Recipient

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"For developing the level-sensitive scan technique of testing solid-state logic circuits and for leading, defining, and promoting design for testability concepts"


Thomas W. Williams is a Chief Scientist at Synopsys. Prior to that Dr. Williams was a Senior Technical Staff Member with IBM Microelectronics Division in Boulder, Colorado, as  manager of the VLSI Design For Testability group, which dealt with design for testability of IBM products. He received a BSEE from Clarkson University, an MA in pure mathematics from the State University of New York at Binghamton, and a Ph.D. in electrical engineering from Colorado State University.

Dr. Williams is engaged in numerous professional activities. He is the founder and chair of the annual IEEE Computer Society Workshop on Design for Testability. He is the co-founder of the European Workshop on Design for Testability. He is also the chair of the IEEE Technical Subcommittee on Design for Testability. He has been a program committee member of many conferences in the area of testing, as well as being a keynote or invited speaker at a number of conferences, both in the U.S. and abroad. He was selected as a Distinguished Visiting Speaker by the IEEE Computer Society from 1982 to 1985. He has been a special-issue editor in the area of design for testability for both the IEEE Transactions on Computers and the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. He has written four book chapters and many papers on testing, edited a book and recently co-authored another book entitled Structured Logic Testing. (with E. B. Eichelberger, E. Lindbloom, and J. A. Waicukauski).

Dr. Williams has received a number of best paper awards, including the 1987 Outstanding Paper Award from the IEEE International Test Conference for his work in the area of VLSI Self-Testing, (with W. Daehn, M. Gruetzner, and C. W. Starke), a 1987 Outstanding Paper Award from the CompEuro'87 for his work on Self-Test, a 1989 Outstanding Paper Award (Honorable Mention) from the IEEE International Test Conference for his work on AC Test Quality (with U. Park and M. R. Mercer), and a 1991 Outstanding Paper Award from the ACM/IEEE Design Automation Conference for his work in the area of Synthesis and Testing (with B. Underwood and M. R. Mercer).

He is an Adjunct Professor at the University of Colorado, Boulder, and in 1985 and 1997  he  was a Guest Professor and Robert Bosch Fellow at the Universitaet of Hannover, Hannover Germany. Dr. Williams was named an IEEE Fellow in 1988, "for leadership and contributions to the area of design for testability."

In 1989, Dr. Williams and Dr. E. B. Eichelberger shared the IEEE Computer Society W. Wallace McDowell Award for Outstanding Contribution to the Computer Art, and was cited "for developing the level-sensitive scan technique of testing solid-state logic circuits and for leading, defining, and promoting design for testability concepts." His research interests are in design for testability (scan design and self-test), test generation, fault simulation, synthesis and fault-tolerant computing.