IEEE Transactions on Multi-Scale Computing Systems
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From the April-June 2017 issue
ARTEMIS: An Aging-Aware Runtime Application Mapping Framework for 3D NoC-Based Chip Multiprocessors
By Venkata Yaswanth Raparti, Nishit Kapadia, and Sudeep Pasricha
In emerging 3D NoC-based chip multiprocessors (CMPs), aging in circuits due to bias temperature instability (BTI) stress is expected to cause gate-delay degradation that, if left unchecked, can lead to untimely failure. Simultaneously, the effects of electromigration (EM) induced aging in the on-chip wires, especially those in the 3D power delivery network (PDN), are expected to notably reduce chip lifetime. A commonly proposed solution to mitigate circuit-slowdown due to aging is to hike the supply voltage; however, this increases current-densities in the PDN due to the increased power consumption on the die, which in turn expedites PDN-aging. We thus note that mechanisms to enhance lifetime reliability in 3D NoC-based CMPs must consider circuit-aging together with PDN-aging. In this paper, we propose a novel runtime framework (ARTEMIS) for intelligent dynamic application-mapping and voltage-scaling to simultaneously manage aging in circuits and the PDN, and enhance the performance and lifetime of 3D NoC-based CMPs. We also propose an aging-enabled routing algorithm that balances the degree of aging between NoC routers and cores, thereby increasing the combined lifetime of both. Our framework also considers dark-silicon power constraints that are becoming a major design challenge in scaled technologies, particularly for 3D stacked CMPs. Our experimental results indicate that ARTEMIS enables the execution of 25 percent more applications over the chip lifetime compared to state-of-the-art prior work.
Editorials and Announcements
- We're pleased to announce that Partha Pratim Pande, professor at Washington State University, has accepted the position of inaugural Editor-in-Chief.
- Editorial (April-June 2017)
- Editorial (Jan-March 2016)
- Introduction to IEEE Transactions on Multiscale Computing Systems (TMSCS) (Jan-March 2015)
- Welcome Message (Jan-March 2015)
- Design and Applications of Neuromorphic Computing System (Oct-Dec 2016)
- Hardware/Software Cross-Layer Technologies for Trustworthy and Secure Computing (July-Sept 2016)
- Emerging Memory Technologies—Modeling, Design, and Applications for Multi-Scale Computing (July-Sept 2015)
- Wearables, Implants, and Internet of Things (April-June 2015)
Nominations for TMSCS Best Paper Award
IEEE Transactions on Multi-Scale Computing Systems (TMSCS) is soliciting nominations for the best paper award. This is a distinguished award and an excellent way for us to recognize papers published in TMSCS. The award is based on general quality, originality, contributions, subject matter, and timeliness. Any paper published in the TMSCS during the last two calendar years preceding the award is eligible for nomination. However, self-nomination is not allowed. Each nominator can nominate one paper only. Please send your nomination to the EIC of TMSCS Partha Pande (firstname.lastname@example.org).
Nomination deadline is 31st March 2017. View PDF.
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