IEEE Transactions on Computers
IEEE Transactions on Computers (TC) is a monthly publication that publishes research in such areas as computer organizations and architectures, digital devices, operating systems, and new and important applications and trends.
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From the October 2017 issue
Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits
By M. Hassan Najafi, David J. Lilja, Marc D. Riedel, and Kia Bazargan
In the paradigm of stochastic computing, arithmetic functions are computed on randomized bit streams. The method naturally and effectively tolerates very high clock skew. Exploiting this advantage, this paper introduces polysynchronous clocking, a design strategy in which clock domains are split at a very fine level. Each domain is synchronized by an inexpensive local clock. Alternatively, the skew requirements for a global clock distribution network can be relaxed. This allows for a higher working frequency and so lower latency. The benefits of both approaches are quantified. Polysynchronous clocking results in significant latency, area, and energy savings for wide variety of applications.
Editorials and Announcements
Editor's pick of the year 2016 (4 selected papers, each one free-to-download for three months in 2017)
- (January-March 2017) - Memory Bandwidth Management for Efficient Performance Isolation in Multi-Core Platforms, by Heechul Yun, Gang Yao, Rodolfo Pellizzoni, Marco Caccamo, and Lui Sha (IEEE Transactions on Computers, Volume: 65, Issue: 2, February 2016, pages 562-576, DOI: 10.1109/TC.2015.2425889).
- (April-June 2017) - Conﬁgurable XOR Hash Functions for Banked Scratchpad Memories in GPUs, by Gert-Jan van den Braak, Juan Gomez-Luna, Jose Marıa Gonzalez-Linares, Henk Corporaal, and Nicolas Guil (IEEE Transactions on Computers, Volume: 65, Issue: 7, July 2016, pages 2045-2058, DOI: 10.1109/TC.2015.2479595).
- (July-September 2017) - Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption, by Xiaolin Cao, Ciara Moore, Maire O’Neill, Elizabeth O’Sullivan, and Neil Hanley (IEEE Transactions on Computers, Volume: 65, Issue: 9, September 2016, pages 2794-2806, DOI: 10.1109/TC.2015.2498606).
- (September-December 2017) - A New Design of In-Memory File System Based on File Virtual Address Framework by Edwin H.-M. Sha, Xianzhang Chen, Qingfeng Zhuge, Liang Shi, and Weiwen Jiang (IEEE Transactions on Computers, Volume: 65, Issue: 10, October 2016, pages 2959-2972, DOI: 10.1109/TC.2016.2516019).
- Editor's pick of the year selection, announced in the July 2016 Editorial
- Multimedia presentations of each monthly featured paper are now available in Chinese, English, and Spanish
- Special Section on Advanced Techniques for Efficient and Reliable Cloud Storage (August 2016)
- Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems (April 2016)
- IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (March 2016)
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A Message from Editor-in-Chief Paolo Montuschi
Importance of Coherence Protocols with Network Applications on Multi-Core Processors
Automated Generation of Performance and Dependability Models for the Assessment of Wireless Sensor Networks