IEEE Transactions on Computers

IEEE Transactions on Computers (TC) is a monthly publication that publishes research in such areas as computer organizations and architectures, digital devices, operating systems, and new and important applications and trends.


TC Seeks Editor-in-Chief for 2019-2021 Term

TC seeks Editor-in-Chief applicants for a three-year term starting 1 January 2019, renewable for two years. Prospective candidates are asked to provide a complete curriculum vitae, a brief plan for the publication's future, and a letter of support from their institution or employer to Kim Sperka, ksperka@computer.org, by 1 March 2018. Please click here for additional information.


Expand your horizons with Colloquium, a monthly survey of abstracts from all CS transactions!


From the May 2018 issue

On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems

By Wonje Choi, Karthi Duraisamy, Ryan Gary Kim, Janardhan Rao Doppa, Partha Pratim Pande, Diana Marculescu, and Radu Marculescu

Featured article thumbnail image Convolutional Neural Networks (CNNs) have shown a great deal of success in diverse application domains including computer vision, speech recognition, and natural language processing. However, as the size of datasets and the depth of neural network architectures continue to grow, it is imperative to design high-performance and energy-efficient computing hardware for training CNNs. In this paper, we consider the problem of designing specialized CPU-GPU based heterogeneous manycore systems for energy-efficient training of CNNs. It has already been shown that the typical on-chip communication infrastructures employed in conventional CPU-GPU based heterogeneous manycore platforms are unable to handle both CPU and GPU communication requirements efficiently. To address this issue, we first analyze the on-chip traffic patterns that arise from the computational processes associated with training two deep CNN architectures, namely, LeNet and CDBNet, to perform image classification. By leveraging this knowledge, we design a hybrid Network-on-Chip (NoC) architecture, which consists of both wireline and wireless links, to improve the performance of CPU-GPU based heterogeneous manycore platforms running the above-mentioned CNN training workloads. The proposed NoC achieves 1.8× reduction in network latency and improves the network throughput by a factor of 2.2 for training CNNs, when compared to a highly-optimized wireline mesh NoC. For the considered CNN workloads, these network-level improvements translate into 25 percent savings in full-system energy-delay-product (EDP). This demonstrates that the proposed hybrid NoC for heterogeneous manycore architectures is capable of significantly accelerating training of CNNs while remaining energy-efficient.

download PDF View the PDF of this article      csdl View this issue in the digital library     TC Featured Article Youtube video  YouTube     TC Featured Article Youtube video in Chinese  YouTube (Chinese)     TC Featured Article on Youku  Youku     TC Featured Article Youtube video in Spanish  YouTube (Spanish)


Editorials and Announcements

Announcements

  • TC now offers authors access to Code Ocean. Code Ocean is a cloud-based executable research platform that allows authors to share their algorithms in an effort to make the world’s scientific code more open and reproducible. Learn more or sign up for free.
  • Multimedia presentations of each monthly featured paper are now available in Chinese, English, and Spanish

Editorials


Guest Editorials


Reviewers List


Annual Index


Access Recently Published TC Articles

RSS Subscribe to the RSS feed of recently published TC content

mail icon Sign up for e-mail notifications through IEEE Xplore Content Alerts

preprints icon View TC preprints in the Computer Society Digital Library


A Message from Editor-in-Chief Paolo Montuschi

 

Importance of Coherence Protocols with Network Applications on Multi-Core Processors

 

Automated Generation of Performance and Dependability Models for the Assessment of Wireless Sensor Networks

Computing Now