IEEE Transactions on Computers
IEEE Transactions on Computers (TC) is a monthly publication that publishes research in such areas as computer organizations and architectures, digital devices, operating systems, and new and important applications and trends.
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From the December 2017 issue
High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes
By Xiaoping Cui, Wenwen Dong, Weiqiang Liu, Earl E. Swartzlander, and Fabrizio Lombardi
A parallel decimal multiplier with improved performance is proposed in this paper by exploiting the properties of three different binary coded decimal (BCD) codes, namely the redundant BCD excess-3 code (XS-3), the overloaded decimal digit set (ODDS) code and the BCD-4221/5211 code. The signed-digit radix-10 recoding is used to recode the BCD multiplier to the digit set [-5, 5] from [0, 9]. The redundant BCD XS-3 code is adopted to generate the multiplicand multiples in a carry-free manner. The XS-3 coded partial products (PPs) are converted to ODDS PPs to fit binary partial product reduction (PPR). In this paper, a regular decimal PPR tree using ODDS and BCD-4221/5211 codes is proposed; it consists of a binary PPR tree block, a non-fixed size BCD-4221 counter block and a BCD-4221/5211 PPR tree block. The decimal carry-save algorithm based on BCD-4221/5211 is used in the PPR tree to obtain high performance multipliers. Moreover, an improved PPG circuit and an improved parallel prefix/carry-select decimal adder are proposed to further improve the performance of the proposed multipliers. Analysis and comparison using the 45 nm technology show that the proposed decimal multipliers are faster and require less hardware area than previous designs found in the technical literature.
Editorials and Announcements
Editor's pick of the year 2016 (4 selected papers, each one free-to-download for three months in 2017)
- (January-March 2017) - Memory Bandwidth Management for Efficient Performance Isolation in Multi-Core Platforms, by Heechul Yun, Gang Yao, Rodolfo Pellizzoni, Marco Caccamo, and Lui Sha (IEEE Transactions on Computers, Volume: 65, Issue: 2, February 2016, pages 562-576, DOI: 10.1109/TC.2015.2425889).
- (April-June 2017) - Conﬁgurable XOR Hash Functions for Banked Scratchpad Memories in GPUs, by Gert-Jan van den Braak, Juan Gomez-Luna, Jose Marıa Gonzalez-Linares, Henk Corporaal, and Nicolas Guil (IEEE Transactions on Computers, Volume: 65, Issue: 7, July 2016, pages 2045-2058, DOI: 10.1109/TC.2015.2479595).
- (July-September 2017) - Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption, by Xiaolin Cao, Ciara Moore, Maire O’Neill, Elizabeth O’Sullivan, and Neil Hanley (IEEE Transactions on Computers, Volume: 65, Issue: 9, September 2016, pages 2794-2806, DOI: 10.1109/TC.2015.2498606).
- (September-December 2017) - A New Design of In-Memory File System Based on File Virtual Address Framework by Edwin H.-M. Sha, Xianzhang Chen, Qingfeng Zhuge, Liang Shi, and Weiwen Jiang (IEEE Transactions on Computers, Volume: 65, Issue: 10, October 2016, pages 2959-2972, DOI: 10.1109/TC.2016.2516019).
- Editor's pick of the year selection, announced in the July 2016 Editorial
- Multimedia presentations of each monthly featured paper are now available in Chinese, English, and Spanish
- Special Section on Emerging Non-Volatile Memory Technologies: From Devices to Architectures and Systems
Submission deadline: 28 Feb. 2018
- Introduction to the Special Issue on Computer Arithmetic (December 2017)
- Special Section on Advanced Techniques for Efficient and Reliable Cloud Storage (August 2016)
- Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems (April 2016)
- IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (March 2016)
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A Message from Editor-in-Chief Paolo Montuschi
Importance of Coherence Protocols with Network Applications on Multi-Core Processors
Automated Generation of Performance and Dependability Models for the Assessment of Wireless Sensor Networks