IEEE Transactions on Computers
IEEE Transactions on Computers (TC) is a monthly publication that publishes research in such areas as computer organizations and architectures, digital devices, operating systems, and new and important applications and trends.
TC Seeks Editor-in-Chief for 2019-2021 Term
TC seeks Editor-in-Chief applicants for a three-year term starting 1 January 2019, renewable for two years. Prospective candidates are asked to provide a complete curriculum vitae, a brief plan for the publication's future, and a letter of support from their institution or employer to Kim Sperka, email@example.com, by 1 March 2018. Please click here for additional information.
Expand your horizons with Colloquium, a monthly survey of abstracts from all CS transactions!
From the March 2018 issue
Hybrid Obfuscation to Protext Against Disclosure Attacks on Embedded Microprocessors
By M. Fyrbiak, S. Rokicki, N. Bissantz, R. Tessier and C. Paar
The risk of code reverse-engineering is particularly acute for embedded processors which often have limited available resources to protect program information. Previous efforts involving code obfuscation provide some additional security against reverse- engineering of programs, but the security benefits are typically limited and not quantifiable. Hence, new approaches to code protection and creation of associated metrics are highly desirable. This paper has two main contributions. We propose the first hybrid diversification approach for protecting embedded software and we provide statistical metrics to evaluate the protection. Diversification is achieved by combining hardware obfuscation at the microarchitecture level and the use of software-level obfuscation techniques tailored to embedded systems. Both measures are based on a compiler which generates obfuscated programs, and an embedded processor implemented in an FPGA with a randomized Instruction Set Architecture (ISA) encoding to execute the hybrid obfuscated program. We employ a fine-grained, hardware-enforced access control mechanism for information exchange with the processor and hardware-assisted booby traps to actively counteract manipulation attacks. It is shown that our approach is effective against a wide variety of possible information disclosure attacks in case of a physically present adversary. Moreover, we propose a novel statistical evaluation methodology that provides a security metric for hybrid-obfuscated programs.
Editorials and Announcements
- TC now offers authors access to Code Ocean. Code Ocean is a cloud-based executable research platform that allows authors to share their algorithms in an effort to make the world’s scientific code more open and reproducible. Learn more or sign up for free.
- Multimedia presentations of each monthly featured paper are now available in Chinese, English, and Spanish
- Special Section on Emerging Non-Volatile Memory Technologies: From Devices to Architectures and Systems - Submission deadline: 28 Feb. 2018
- State of the Journal (Jan 2018)
- State of the Journal (Jan 2017)
- State of the Journal (July 2016)
- State of the Journal (Jan 2016)
- Special Section on Secure Computer Architectures (March 2018)
- Introduction to the Special Issue on Computer Arithmetic (December 2017)
- Special Section on Advanced Techniques for Efficient and Reliable Cloud Storage (August 2016)
- Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems (April 2016)
- IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (March 2016)
Access Recently Published TC Articles
Subscribe to the RSS feed of recently published TC content
Sign up for e-mail notifications through IEEE Xplore Content Alerts
View TC preprints in the Computer Society Digital Library
A Message from Editor-in-Chief Paolo Montuschi
Importance of Coherence Protocols with Network Applications on Multi-Core Processors
Automated Generation of Performance and Dependability Models for the Assessment of Wireless Sensor Networks