A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories
AUG 01, 2017 16:48 PM
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A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories

A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories

Wei Wei, Department of Electrical and Computer Engineering, Northeastern University, Boston, MA
Kazuteru Namba, Graduate School of Advanced Integration Science, Chiba University, Chiba, Japan
Yong-Bin Kim, Department of Electrical and Computer Engineering, Northeastern University, Boston, MA
Fabrizio Lombardi, Department of Electrical and Computer Engineering, Northeastern University, Boston, MA

This article proposes a novel scheme for a low-power non-volatile memory that exploits a two-level arrangement for attaining single event/multiple bit upsets tolerance.

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