Ramesh Karri

Ramesh Karri Ramesh Karri (2013-2015)
Specializations: VLSI Test and Trust; Trustworthy Hardware; Cyber Meets Nano
Office: 718 260 3596
Cell: 917 363 9703
Email:  rkarri {@} poly.edu

Ramesh Karri (http://eeweb.poly.edu/karri/) is a Professor of Electrical and Computer Engineering at Polytechnic Institute of New York University. He has a Ph.D. in Computer Science and Engineering, from the University of California at San Diego. His research interests include trustworthy ICs and processors; High assurance nanoscale architectures and systems; VLSI Design for Test and Trust; Interaction between security and reliability.


He has over 150 journal and conference publications in these areas. He has written two invited articles in IEEE Computer on Trustworthy Hardware, an invited article on Digital Logic Design using Memristors in Proceedings of IEEE and an Invited article in IEEE Computer on Reliable Nanoscale Systems.


He was the recipient of the Humboldt Fellowship and the National Science Foundation CAREER Award. He is the area director for cyber security of the NY State Center for Advanced Telecommunications Technologies at NYU-Poly; Hardware security lead of the Center for research in interdisciplinary studies in security and privacy -CRISSP (http://crissp.poly.edu/), co-founder of the Trust-Hub (http://trust-hub.org/) and organizes the annual red team blue team event at NYU, the Embedded Systems Challenge (http://www.poly.edu/csaw2012/csaw-embedded). He served on the 2006 DARPA ISAT study on "Trust in Integrated Circuits".


He cofounded and served as the chair of the IEEE Computer Society Technical Committee on Nanoscale architectures. He is a cofounder and steering committee member of the IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH). He is the Program Chair (2012) and General Chair (2013) of IEEE Symposium on Hardware Oriented Security and Trust (HOST). He is the Program Co-Chair (2012) and General Co-Chair (2013) of IEEE Symposium on Defect and Fault Tolerant Nano VLSI Systems. He is the General Chair of the 2013 NANOARCH. He serves on several program committees including DAC 2013, ICCD 2012-2013, VTS 2014 and VLSI-SoC 2013. He is an Associate Editor of IEEE Transactions on Information Forensics and Security and an Associate Editor of ACM Journal on Emerging Computing Technologies. He is a Distinguished Lecturer of IEEE Computer Society for 2013-2105.


He has presented invited tutorials on various aspects of Trustworthy Hardware including at 2012 VLSI Test Symposium, 2012 International Conference on Computer Design, 2013 IEEE North Atlantic Test Workshop, 2013 Design Automation and Test in Europe.


Talk 1: Trustworthy Hardware (60 minutes or half day or full day tutorial style)

Hardware security and trust is an important design objective similar to power, performance, reliability and testability. I will highlight why hardware security and trust are important objectives from the economics, security, and safety perspectives. Important learning outcomes of this talk include (i) understanding simple gotchas when traditional DFT, test, and validation techniques are used (scan chains, JTAG, SoC test, assertion based validation), (ii) understand how traditional DFT, test and validation techniques can be used to improve hardware security and trust and finally (iii) understand "Design for Trust" approaches that can provide testability without compromising security and trust.

Talk 2: A red team blue team approach to hardware trust assessment (60 minutes or half day hands on tutorial using software simulators, FPGA hardware platforms and ESC Trojan artifacts).

Hardware security techniques are validated using fixed in-house methods. However, the effectiveness of such techniques is limited to the static faults or detection of prior attacks. In contrast, a red team blue team approach is ideal when the attack scenarios are dynamic. They can be used to validate defenses by determining the effectiveness of a defense and identifying vulnerabilities in it. We will discuss this emerging approach that complements manufacture testing to detect hardware Trojans and fix vulnerabilities in designs. I will use case studies from the Annual Embedded Systems Challenges (ESC) that we organized over the last five years to provide insights into the scalable hardware vulnerability assessment approaches.

Talk 3: Cyber meets nano: Cyber Security Exploiting Emerging Nanoelectronics (60 minutes or half day tutorial)

Hardware security has emerged as an important field of study aimed at mitigating issues such as piracy, counterfeiting, and side channel attacks. One popular solution for such hardware security attacks are physical unclonable functions (PUF) which provide a hardware specific unique signature or identification. The uniqueness of a PUF depends on intrinsic process variations within individual integrated circuits. As process variations become more prevalent due to technology scaling into the nanometer regime, novel nanoelectronic technologies such as memristors become viable options for improved security in emerging integrated circuits. In this talk, I will provide an overview of memristor based PUF structures and circuits that illustrate the potential for nanoelectronic hardware security solutions.