IEEE Transactions on Multi-Scale Computing Systems

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From the July-September 2017 issue

Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC)

By Linbin Chen, Jie Han, Weiqiang Liu, and Fabrizio Lombardi

Featured article thumbnail imageThis paper proposes a new approximate scheme for coordinate rotation digital computer (CORDIC) design. This scheme is based on modifying the existing Para-CORDIC architecture with an approximation that is inserted in multiple parts and made possible by relaxing the CORDIC algorithm itself. A fully parallel approximate CORDIC (FPAX-CORDIC) scheme is proposed. This scheme avoids the memory register of Para-CORDIC and makes the generation of the rotation direction fully parallel. A comprehensive analysis and the evaluation of the error introduced by the approximation together with different circuit-related metrics are pursued using HSPICE as the simulation tool. This error analysis also combines existing figures of merit for approximate computing (such as the Mean Error Distance (MED) and MED Power Product (MPP)) with CORDIC specific parameters. It is shown that a good agreement between expected and simulated error values is found. The Discrete Cosine Transformation (DCT) and the Inverse DCT (IDCT) transformations as case study of approximate computing to image processing are investigated by utilizing the proposed approximate FPAX-CORDIC architecture with different accuracy requirements. The results confirm the viability of the proposed scheme.

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Editorials and Announcements

Announcements

  • The winner of the 2017 Best TMSCS Paper Award is:
    "Enabling New Computation Paradigms with HyperFET - An Emerging Device"
    by Wei-Yu Tsai, Xueqing Li, Matthew Jerry, Baihua Xie, Nikhil Shukla, Huichu Liu, Nandhini Chandramoorthy, Matthew Cotter, Arijit Raychowdhury, Donald M Chiarulli, Steven P Levitan, Suman Datta, John Sampson, Nagarajan Ranganathan, Vijaykrishnan Narayanan
    IEEE Transactions on Multi-Scale Computing Systems, Vol. 2, Iss. 1, pp. 30-48, 2016.
  • We're pleased to announce that Partha Pratim Pande, professor at Washington State University, has accepted the position of inaugural Editor-in-Chief.

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Special Issue on Advances in High-Performance Interconnects

Submission deadline: 1 Jan. 2018. View PDF.

High-performance interconnects have had a major role in high-performance scientific computing for several decades. They are also gaining traction in cloud computing and massive traditional data centers. The intersection of high-performance interconnects between these two areas spans networks of all scales, from small on-chip interconnects to whole system interconnects with hundreds of thousands of links. Innovation of new network architectures both in terms of software and hardware systems is a key component in next generation systems. As the number of cores in a single node increases, the bandwidth and message rates required from a single network interface controller (NIC) has continued to rise rapidly. Improvements to NIC architectures are required in order to keep up with increasing core counts on CPUs. In addition, improvements in network topologies have driven down costs by reducing the number of links and switches required to provide very high performance. These changes have also introduced interesting challenges as innovation in network topologies requires adopting adaptive routing and advanced congestion avoidance mechanisms. This special issue concentrates on the latest cutting edge developments in interconnects from both the cloud/data center and scientific computing communities.

This special issue invites original research papers and extended papers from the 25th Annual Symposium on High-Performance Interconnects that showcase cutting-edge research on hardware and software architectures and implementations for interconnection networks of all scales.

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