IEEE Transactions on Emerging Topics in Computing

Covering aspects of computer science, computing technology, and computing applications not currently covered by other IEEE Computer Society Transactions

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From the July-September 2017 issue

Performance Enhancement of a Time-Delay PUF Design by Utilizing Integrated Nanoscale ReRAM Devices

By Karsten Beckmann, Harika Manem, and Nathaniel C. Cady

Currently the semiconductor industry is in search of a Physically-Unclonable-Function (PUF) implementation, which combines high reliability and uniqueness with low area and power consumption. The characteristics of emerging nanoscale Resistive Random Access Memory (ReRAM) devices fulfill most of these properties, as they exhibit inherent variability with low area consumption. Of particular interest is that the resistive states of ReRAM devices show a strong dependence on the distribution of grain boundaries within the device, which leads to variability in total device resistance. In this work we transform the classic CMOS time-delay PUF (TD-PUF) utilizing integrated nanoscale ReRAM devices to achieve better performance metrics including uniqueness and reliabilitiiy. The enhanced design exploits the property of high resistance variability of ReRAMs for the design of a ReRAM based delay stage that exhibits excellent uniqueness. Accurate simulation and characterization of the proposed PUF was achieved by extracting resistance values, temperature dependence and usage stress of ReRAM devices fabricated in-house and their application in the proposed TD-PUF are discussed. A 24 stage time-delay PUF utilizing 48 ReRAM devices was simulated and results show excellent reliability with respect to environmental parameters. A temperature range of 0 to 125°C was simulated and an optimum reliability was observed at 0.79 V. A supply voltage noise of ±30 mV had no impact on the uniqueness and reliability. The proposed design was compared against two pure CMOS implementations of a TD-PUF. The comparison was performed with respect to the aforementioned metrics and under the same environmental conditions, showing up to 5 times increase in performance.

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Editorials and Announcements


  • We are pleased to announce that Cecilia Metra, a Confirmed Full Professor in Electronics at the University of Bologna, Italy, has been named the new Editor-in-Chief of TETC starting in 2018.
  • TETC has been included in the Clarivate Analytics Journal Citation Reports (JCR) 2016 Edition with the following results:
    • Impact Factor: 3.826
    • Eigenfactor: 0.00181
    • Article Influence Score: 1.073
    All TETC articles dating back to the first 2013 issue will be indexed and abstracted in:
    • Science Citation Index Expanded (also known as SciSearch®)
    • Journal Citation Reports/Science Edition
    • Current Contents®/Engineering Computing and Technology
  • TETC Tips and Tricks - FAQ for S1M Submissions (PDF)
  • TETC Special Issue/Section Proposal Information Rules (PDF)
  • Beginning in 2015, IEEE Transactions on Emerging Topics in Computing has moved to our hybrid open access publishing model. Authors can now select between either Traditional manuscript submission or Open Access (author-pays OA) manuscript submission. Learn more.
  • A Welcome Letter from Thomas M. Conte (PDF)


Guest Editorials

Reviewers list

Author Index

Call for Papers

Technical Tracks

View PDF.

IEEE Transactions on Emerging Topics in Computing (TETC) seeks original manuscripts for submission under Technical Tracks. In a track the technical contents of a submitted manuscript must be of an emerging nature and fall within the scope and competencies of the Computer Society. Manuscripts not abiding by these specifications will be administratively rejected. The topics of interest for the Technical Tracks are as follows:

  • Enterprise Computing Systems
  • Computational Networks
  • Hardware and Embedded System Security
  • Educational Computing
  • High Performance Computing
  • Next Generation Wireless Computing Systems
  • Computer System Security
  • Emerging Hardware for Computing

Submitted articles must describe original research which is not published or currently under review by other journals or conferences. Extended conference papers should be identified in the submission process and have considerable novel technical content; all submitted manuscripts will be screened using a similarity checker tool. As an author, you are responsible for understanding and adhering to our submission guidelines. You can access them at the IEEE Computer Society web site, Please thoroughly read these before submitting your manuscript.

Please submit your paper to Manuscript Central at and select the "Technical Track" option in the drop-down menu for "Manuscript Type".

Please address all other correspondence regarding this Call For Papers to Fabrizio Lombardi, EIC of IEEE TETC,

Special Issue on Scholarly Big Data

Submission deadline: December 1, 2017. View PDF.

Recent years have witnessed the rapid growth of scholarly information due to advancements in information and communication technologies. Scholarly big data is the vast quantity of research output, which can be acquired from digital libraries, such as journal articles, conference proceedings, theses, books, patents, experimental data, etc. It also encompasses various scholarly related data, such as author demography, academic social networks, and academic activity. The abundance of scholarly data sources enables researchers to study the academic society from a big data perspective. The dynamic and diverse nature of scholarly big data requires different data management techniques and advanced data analysis methods. Today’s researchers realize that new scholarly-big-data specific platform/management/techniques/ are needed. Therefore, a set of emerging topics such as scholarly big data acquisition, storage, management and processing are important issues for the research community. Manuscripts submitted to TETC should be computing focused.

This special issue focuses on covering the most recent research results in scholarly big data management and computing. The issue welcomes both theoretical and applied research (e.g. platforms and applications). It will encourage the effort to share data, advocate gold-standard evaluation among shared data, and promote the exploration of new directions.

Special Issue on Design of Reversible Computing Systems

Submission deadline: March 1, 2018. View PDF.

IEEE Transaction on Emerging Topics in Computing (TETC) seeks original manuscripts for a Special Issue/Section on Design of Reversible Computing Systems scheduled to appear in the first issue of 2019.

Over the coming decade, the historical trend of exponentially-increasing computer performance for systems at a given cost level is expected to slow, as conventional digital technology approaches practical limits to its computational energy efficiency, which in turn limits system performance within any given power and cooling constraints. In the long term, due to fundamental connections between thermodynamics and information theory, the only possible way to continue improving the energy-efficiency and affordable performance of computing systems indefinitely is if their designs increasingly thoroughly apply reversible computing principles. However, the question of exactly how to design practical, cost-competitive reversible computing systems is an extremely challenging engineering problem, which today still remains far from being fully solved. To overhaul the existing industrial infrastructure of manufacturing processes, design tools and software in all of the ways that will likely be needed to fully realize the potential of this unconventional but essential new computing paradigm will arguably require a multi-billion-dollar sustained investment in associated research and development activities. We cannot assume this investment will be made until the research community builds a sufficiently solid case showing that workable implementation approaches exist and are economically feasible. It is the goal of this special issue to solicit high-quality contributions across all levels of computing that pointedly address the crucial issues in the theory, design, and engineering analysis of reversible computing systems, so as to eliminate all of the remaining conceptual roadblocks that impede investment, and establish that the reversible computing paradigm indeed provides a viable path forwards, towards an unbounded new future for computing.

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