Call for Papers

IEEE Design & Test of Computers

 

Special Issue on Yield Learning Processes and Methods

January/February 2012

Guest Editors: Anne Gattiker and Phil Nigh, IBM


IC manufacturing provides growing challenges as manufacturing complexity increases as technology development cycles are reduced. The industry is at the point now where many failure modes cannot be anticipated prior to manufacturing. Failures occur from complex interactions among physical design features that cannot be anticipated with test or monitor chips. As a result, understanding failures based on real products is crucial. Moreover, old methods of understanding failures based on physical failure analysis are no longer tenable, given the ‘‘nonvisual’’ nature of many defects, and the increasing reliance on diagnosis as a part ofmanufacturing bringup. This issue proposes to address yield learning in this new era of manufacturing complexity, with emphasis on products as the vehicles for that learning.

IEEE Design & Test
seeks original contributions on the following topics for this special issue:

  • High-volume logic diagnostics techniques
  • Using volume diagnostic data to understand yield loss
  • Methods to distinguish systematic from random defect mechanisms
  • Diagnostic methods
  • Defect-type changes with advanced technology nodes
  • DFT features to support yield learning
  • On-chip sensors—methods that drive yield learning
  • Power/performance analysis methods for yield optimization
  • Critical-path analysis to enable yield optimization


Submission and review procedures

Prospective authors should follow the submission guidelines for IEEE Design & Test. All manuscripts must be submitted electronically to the IEEE Manuscript Central Web site at https://mc.manuscriptcentral.com/cs-ieee. Indicate that you are submitting your article to the special issue on ‘‘Yield Learning Processes and Methods.’’ All articles will undergo the standard IEEE Design & Test review process. Submitted manuscripts must not have been previously published or currently submitted for publication elsewhere. Manuscripts must not exceed 5,000 words, including figures (with each average-size figure counting as 200 words) and a maximum of 12 References (30 for surveys). This amounts to about 4,000 words of text and a maximum of five small to medium figures. Accepted articles will be edited for clarity, structure, conciseness, grammar, logical organization, readability, and adherence to D&T and Computer Society style.

Please see IEEE D&T Author Resources at http://www.computer.org/dt/author.htm, then scroll down and click on Author Center for submission guidelines and requirements.

Schedule

Articles due for review: 1 May 2011
Reviews completed: 1 July 2011
Article revisions due: 1 Aug. 2011
Notice of final acceptance: 1 Sept. 2011
All materials due for edit: 1 Oct. 2011
Publication date: January/February 2012

Questions?

Please direct questions regarding this special issue to Guest Editors Anne Gattiker (gattiker@us.ibm.com) and Phil Nigh (nigh@us.ibm.com).