IEEE Design & Test of Computers, March/April 2009

Hybrid BIST Scheme for Multiple Heterogenous Embedded Memories

Hybrid BIST Scheme for Multiple Heterogenous Embedded Memories

by Li-Ming Denq, Yu-Tsao Hsing, and Cheng-Wen Wu

Embedded memories are widely used in SoCs. Unfortunately, the high density and capacity of embedded memories make them more prone to manufacturing defects than logic circuits. To increase SoC yield and reliability and reduce the yield ramp-up period, efficient testing and diagnostic methodologies for embedded memory are necessary. Accessing the embedded RAMs from an external tester is costly—in terms of pin overhead, performance penalty, and timing accuracy issues. Because testing embedded memories using external ATE would require an excessive amount of primary I/O pins, and at-speed testing would be difficult to achieve, BIST is more practical for embedded-memory testing and diagnosis.

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