Goals

The IEEE Computer Society Special Technical Community on MultiCore (STCMC) aims at promoting research, development, education, and standard activities related to multicore and manycore technologies by providing places for discussion to communities from academia, industry, and government.

Activities will include leader summits, international conferences, workshops, online lectures, online magazines and transactions, and working with standard committees.

The STC on MultiCore tries to fuse the multicore hardware, software, and application communities of the embedded fields, including

  • smart phones
  • tablets
  • cameras
  • TV broadcasts
  • movies
  • games
  • medical systems
  • automobiles
  • airplanes and so on.


These embedded fields may be part of the personal computer and server fields, such as  home servers, cloud servers and up to the exa-scale supercomputers, and used for basic sciences, devices, natural disaster simulations, medical computations, space developments, financial engineering and so on through common objectives for high performance, low power, reliability, low software development costs and periods.

This STC has just started the above activities. Many kinds of proposals for the above objectives from the communities are welcome. Please join and create the MultiCore STC together.

 

Keywords

multicore, manycore, heterogeneous, low power, high performance, reliability, embedded, supercomputer, architecture, language, API, compiler, OS, I/O, library, tuning, debugging, smart phone, automobile, medical, device, weather, energy, space, finance

 

News

Jan. 14, 2017

Strategic Computing Initiative Workshop SISA2017 with World Leading Researchers will 

be held in Waseda Green Computing Center on Jan.18 and 19, 2017.

 

 

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International Workshop on A Strategic Initiative of Computing: Systems and Applications (SISA): Integrating HPC, Big Data, AI and Beyond

 

http://www.sgu-ictrobotics.sci.waseda.ac.jp/en/sisa/index.php

 

Date:   January 18-19, 2017

Place:   Green Computing Systems Research and Development Center, Waseda University

Participant fee:   None

Sponsors:   Waseda University international collaboration research in MEXT SGU Embodiment

                   Informatics Project and Waseda University Advanced Multicore Research Institute

Cooperated by:   IEEE Computer Society Japan Chapter

                            IEEE Computer Society Multicore STC

                            IEEE Computer Society Dataflow STC

Industry Sponsor:   Fujitsu Limited

 

Motivation of the workshop

High-performance computers and big-data systems are tied inextricably to the broader computing ecosystem and its designs and markets. However, during the past decade the eco-systems (the programming models, the system software stack, the software tools, etc.) of high-performance computing and big data appear to have been significantly diverged. Such divergence also presents serious challenges to computing architecture and hardware eco-system as well. Such situation has raised significant concerns: many felt that further divergence may be detrimental to both. In particular, both HPC and big-data systems are also facing challenges from the innovations in AI and computational machine learning methods that must be efficiently and securely handled by both.

 

Workshop goal

To address these concerns we must study the related open R&D problems that are shared by both HPC and Big-Data systems. The technical topics of this workshop have a system focus on the challenges and opportunities from relevant core technology and applications including novel methods from AI and machine learning. The theme goes beyond supercomputing performance issues and includes talks on the challenges and opportunities from demand of global green computing and security needs -- in ways that distinguish them from most other scientific instruments. This workshop provides a unique opportunity to discuss open problems and potential solutions together under the same roof that will have far-reaching impact to future HPC and Big-Data systems, and beyond.

 We recognize that the challenges are real and the stake is high for global community. And it is far beyond the borders of nations and continents, and we should strongly encourage international participation. We also recognize that besides the traditional leadership in the HPC field (US, EU, Japan), the world has witnessed rapid new advance in other regions such as in Asia: China, India, South Korea, Taiwan to name a few. We hope that this workshop will break new ground on international collaborations inspiring future global exchanges and coordination between the emerging centers in Asia and the established centers in US and Europe.

 

Workshop Co-Chairs

  • Guang R. Gao (Chair)   (University of Delaware, USA)
  • Hironori Kasahara (Co-Chair)   (Waseda University, Japan)

Board of Advisors

  • Kimihiko Hirao   (RIKEN, Japan)
  • Masaru Kitsuregawa   (NII and University of Tokyo, Japan)
  • Katsuhiko Shirai   (The Open University of Japan)
  • Shigeki Sugano   (Waseda University, Japan)
  • Thomas Sterling   (University of Indiana, USA)
  • Rick Stevens   (Argonne National Laboratory, USA)

 

Program

*** January 18, 2017 ***

8:15 Opening 

Morning session: Architecture and Application 

8:30 – 9:30 Keynote session: "The Synergy of HPC and Deep Learning"

 by William J. Dally, NVIDIA & Stanford University, USA  

9:30 – 9:45 Break 

9:45 – 10:30 Kimihiko Hirao, RIKEN, Japan 

10:30 – 10:55 Guangwen Yang, Tsinghua University, China 

10:55 – 11:20 James Sexton, IBM, USA 

11:20 – 11:30 Break 

11:30 – 12:30 Panel I (Chairs: G. Gao/H. Kasahara)

Panel list: W.J. Dally, M. Sato, G.W. Yang, J. Sexton  

12:30 – 14:00 Lunch 

Afternoon session: System Software and Applications 

14:00 – 15:00 Keynote session: "Cancer Computing: Driving Architectural Convergence of HPC, Big Data and Deep Learning"

 by Rick Stevens, Argonne National Laboratory, USA  

15:00 – 15:10 Break 

15:10 – 15:35 Mikhail Smelyanskiy, Intel, USA 

15:35 – 16:00 Frederick Streitz, Lawrence Livermore National Laboratory, USA 

16:00 – 16:25 Ramaswamy Govindarajan, Indian Institute of Science, India 

16:25 – 16:50 Hironori Kasahara, Waseda University, Japan 

16:50 – 17:00 Break 

17:00 – 18:00 Panel II  (Chairs: G. Gao/H. Kasahara)

Panel list:  R. Stevens, M. Smelyanskiy, F. Streitz, R. Govindarajan, H. Kasahara

 

*** January 19, 2017 ***

Morning session: Extreme Scale and Beyond 

8:30 – 9:30 Keynote session: "The U.S. D.O.E. Exascale Computing Project – Goals and Challenges"

 by Paul Messina, Argonne National Laboratory, USA  

9:30 – 9:45 Break 

9:45 – 10:10 Motoaki Saito, PEZY, Japan 

10:10 – 10:35 Eiji Ishida, MEXT, Japan 

10:35 – 11:00 Depei Qian, Beihang University, China 

11:00 – 11:25 Toshiyuki Shimizu, Fujitsu, Japan 

11:25 – 11:35 Break 

11:35 – 12:35 Panel III  (Chairs: R. Stevens/T. Sterling)

Panel list:  P. Messina, M. Saito, E.Ishida, D. Qian, N. Shinjo  

12:45 – 14:00 Lunch 

Afternoon session: Integration of HPC, Big Data, and AI 

14:00 – 15:00 Keynote session: "Runtime System Architecture for Dynamic Graph Processing"

 by Thomas Sterling, Indiana University, USA  

15:00 – 15:15 Break 

15:15 – 16:00 Masaru Kitsuregawa, University of Tokyo, Japan 

16:00 – 16:25 Thomas Schulthess, Swiss Federal Institute of Technology (ETH), Switzerland 

16:25 – 16:50 Moriyuki Takamura/Toshiaki Kitamura, Oscar Tech, Japan 

16:50 – 17:00 Break 

17:00 – 18:00 Panel IV  (Chairs: G. Gao/H. Kasahara)

Panel list:  T. Sterling, M. Kitsuregawa, T. Schulthess, M. Takamura

 

 

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Video lectures on "Multicore Compiler" is available from Computer Society.

 

Announcement from IEEE Computer Society Multicore STC

for Video Making for “Lectures on Multicore Compiler”

on September 6 and 7, 2014

in University of Illinois at Urbana-Champaign

 

IEEE Computer Society Multicore STC will make a video lecture course for “Multicore Compiler” with World Leading Researchers representing each compiler technology in Thomas M. Siebel Center for Computer Science in University of Illinois at Urbana-Champaign on September 6 and 7. The details on the lectures are available below or here.

The  "Multicore Compiler" lecture videos will be available from the IEEE Computer Socieity early next year.

A limited number of the seats for the lectures for free are available for Registered Multicore STC members who wish to participate the video making as audience to make questions to improve the content quality. If you are interested in the participation, please join the STC member from this page and send e-mail directly

To: kasahara@waseda.jp,sec@kasahara.cs.waseda.a.jp,dominic.hillenbrand@gmail.com .

 

Prof. Hironori Kasahara, Waseda Univ.

IEEE Computer Society            

BoG Member and Multicore STC Chair

 

Time Schedule for Video Making

Saturday, September 6, 2014

 8:30-8:45        Opening Address    Hironori Kasahara, IEEE Multicore STC Chair, Waseda U

 9:00-10:00      Overview                 David Kuck, IEEE CS Multicore STC Advisory Committee Chair, Intel

 10:30-11:30    Dependences and Dependence Analysis Utpal Banerjee, UC Irvine

 12:00-1:30      Lunch

 1:30- 2:30       The Polyhedral Model Paul Feautrier, Ecole Normale Supérieure de Lyon

 3:00-4:00 Vectorization P. Sadayappan, Ohio State U

 4:30-5:30 Parallelization David Padua, UIUC

Sunday, September 7

 8:00-9:00        Autoparallelization for GPUs                                 Wen-Mei Hwu, UIUC

 9:30-10:30      Instruction Level Parallelization                             Alexandru Nicolau, UC Irvine

 11:00-12:00    Multigrain Parallelization and Power Reduction Hironori Kasahara, Waseda U

 12:30-1:30      Lunch

 1:30-2:30        Dynamic Parallelization                                          Rudolf Eigenmann, Purdue U, NSF

 3:00-3:30        Vectorization/Parallelization in the Intel Compiler  Peng Tu, Intel

 4:00-4:30        Vectorization/Parallelization in the IBM Compiler   Yaoqing Gao, IBM

 5:00-6:30        Round Table All speakers

 

Special Technical Committee Chair
Prof. Hironori Kasahara
Computer Society Board of Governor
Waseda University

Secretary
Prof. Eduardo Juárez Martínez

Universidad Politécnica de Madrid

Dr. Jun Shirako
Rice University

Advisory Committee

Chair
Dr. David Kuck


Intel

Prof. Arvind

Massachusetts Institute of
Technology
Dr. John Walz Computer Society 2012 President

 

Steering Committee

Co-chair
Prof. David Padua

University of Illinois
at Urbana-Champaign

Prof. Thomas
Conte

Georgia Institute
of Technology

Prof. Wen-Mei
Hwu
University of Illinois at
Urbana-Champaign
Prof. Vivek Sarkar
Rice University
Moriyuki
Takamura
Fellow Fujitsu
Laboratories
Prof. Josep
Torrellas
University of Illinois at
Urbana-Champaign
Prof. Jean-Luc Gaudiot University of California,
Irvine 
Dr. Ahmed Jerraya CEA-LETI, MINATEC
Prof. Katherine A. Yelick University of California at Berkeley