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<p>The trace assertion method is a module interface specification method based on the finite state machine model. To support this method, we plan to develop a specification simulation tool, a trace simulator, that symbolically interprets trace assertions of trace specifications and simulates the externally observable behavior of the modules specified. We first present the trace assertion method. Then we formally define trace rewriting systems and show how trace rewriting, a technique similar to term rewriting, can be applied to implement trace simulation.</p>
finite state machines; rewriting systems; formal specification; simulation; digital simulation; software module behavior simulation; trace rewriting; trace assertion method; module interface specification method; finite state machine model; specification simulation tool; trace simulator; trace specifications; trace rewriting systems; term rewriting; trace simulation

D. Parnas and Y. Wang, "Simulating the Behavior of Software Modules by Trace Rewriting," in IEEE Transactions on Software Engineering, vol. 20, no. , pp. 750-759, 1994.
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