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<p>The presence of high-performance mechanisms in shared-memory multiprocessors such as private caches, the extensive pipelining of memory access, and combining networks may render a logical concurrency model complex to implement or inefficient. The problem of implementing a given logical concurrency model in such a multiprocessor is addressed. Two concurrency models are considered, and simple rules are introduced to verify that a multiprocessor architecture adheres to the models. The rules are applied to several examples of multiprocessor architectures.</p>
memory access dependencies; shared-memory multiprocessors; private caches; pipelining; logical concurrency model; rules; multiprocessor architectures; multiprocessing systems; multiprogramming; storage allocation.
M. Dubois, C. Scheurich, "Memory Access Dependencies in Shared-Memory Multiprocessors", IEEE Transactions on Software Engineering, vol. 16, no. , pp. 660-673, June 1990, doi:10.1109/32.55094
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