Issue No. 05 - May (1988 vol. 14)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/32.6137
<p>In current microcode generation systems, one simplification that is frequently made is to assume an absence of timing restrictions. It is critical that timing is considered when the target architecture involves branch delays, volatile registers, or microoperations requiring multiple microinstructions to complete. A general form for representing synchronous timing in clocked microarchitectures and methods of compacting data-dependency graphs with general timing are described.</p>
compilers; general synchronous timing; microcode generation systems; target architecture; branch delays; volatile registers; microoperations; multiple microinstructions; clocked microarchitectures; data-dependency graphs; microprogramming; program compilers; synchronisation
R. Mueller and V. Allen, "Compaction with General Synchronous Timing," in IEEE Transactions on Software Engineering, vol. 14, no. , pp. 595-599, 1988.