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ISSN: 1545-5971
Kyuseung Han , Seoul National University, Seoul
Ganghee Lee , Samsung Electronics Co., Gyeonggi
Kiyoung Choi , Seoul National University, Seoul
Coarse-grained reconfigurable architectures have drawn increasing attention due to their merits in performance and flexibility. Typically, they have many processing elements in the form of an array, which is suitable for implementing spatial redundancy used for fault-tolerant systems design. This paper presents a purely software-level approach to implementing transient-fault-tolerance on an existing processing element array without any modification to the architecture. It includes automated design flow to construct a fault-tolerant system and mathematical modeling for analyzing system reliability. Experiments with real-world applications show the effectiveness of the proposed approaches in terms of system reliability.
Reconfigurable hardware, Redundant design, Array and vector processors

K. Han, G. Lee and K. Choi, "Software-Level Approaches to Implementing Fault-Tolerant Systems on Coarse-Grained Reconfigurable Architecture," in IEEE Transactions on Dependable and Secure Computing.
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